PMOS HKMG Work Function Layer for Flatband Voltage Control
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Solution Overview
Problem
Challenges in achieving desired bandedge performance in PMOS high-k metal gate (HKMG) stacks due to significant flatband voltage (Vfb) rolloff, particularly with Fermi level pinning in advanced device scaling.
Innovation Solution
Incorporating a depinning layer with metals like Al, Ta, Ti, Mo, W, V, Nb, Ru, Sb, and Sn between a high-K dielectric layer and a P-metal layer to minimize flatband voltage rolloff, along with a barrier layer to stabilize the structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PMOS high-k metal gate stack is used, then the device structure is simple, but the flatband voltage rolloff is significant and bandedge performance is poor
Solution Approach 1:
The gate stack is segmented into multiple functional layers: interfacial layer, high-k dielectric layer, depinning layer, P-metal layer, and barrier layer. Each layer performs a specific function, with the depinning layer specifically designed to address the flatband voltage rolloff issue by providing a work function of 4.4-4.7 eV, thus improving bandedge performance without requiring a complete redesign of the entire stack.
Solution Approach 2:
The gate stack employs composite materials with different properties stacked together. The high-k dielectric layer provides high capacitance, the depinning layer provides the appropriate work function, and the barrier layer prevents diffusion. This composite structure allows each material to contribute its optimal properties, resolving the contradiction between performance and complexity.
2Reliability
If the depinning layer is added to improve flatband voltage, then the bandedge performance is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The depinning layer is designed with specific parameter ranges: work function of 4.4-4.7 eV and thickness of 1-10 nm. By controlling these parameters, the layer provides the necessary flatband voltage improvement while maintaining compatibility with existing deposition processes, thus balancing performance improvement with manufacturing ease.
3Productivity
If advanced device scaling is pursued, then functional density increases, but Fermi level pinning becomes more significant
Solution Approach 1:
The depinning layer acts as an intermediary between the high-k dielectric layer and the P-metal layer. It mediates the Fermi level alignment issue that becomes critical at advanced scales by providing a work function (4.4-4.7 eV) that prevents Fermi level pinning, thus maintaining flatband voltage control even as device dimensions are reduced and functional density increases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The depinning layer enhances the flatband voltage by over 100 mV, providing a mid-gap work function of 4.4 to 4.7 eV, thus improving the bandedge performance of PMOS stacks.
Implementation Method 1
the depinning layer having a work function about 4.4 eV to about 4.7 eV
Implementation Method 2
depositing a high-K dielectric layer on the interfacial layer
Data Source
AI summary
Methods of manufacturing semiconductor devices are described. Embodiments of the disclosure advantageously provide semiconductor devices which comprise a PMOS high-k metal gate (HKMG) stack having a depinning layer to achieve the desired bandedge performance because of the significant flatband voltage (Vfb) rolloff. The semiconductor devices described comprise a channel separating a source region and a drain region, an interfacial layer on the channel, a high-K dielectric layer on the interfacial layer, a depinning layer on the high-K dielectric layer, a P-metal layer on the depinning layer, and a barrier layer on the depinning layer.