PMOSFET Gate Electrode Composition for Threshold Voltage Control

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Solution Overview

Problem

The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices negatively affects operational properties, necessitating improvements in electrical and reliability characteristics to maintain high performance.

Innovation Solution

The semiconductor device incorporates a unique gate electrode structure with alternating inner and outer gate electrodes, featuring different concentrations of aluminum or silicon, and a fin structure formed by alternately stacking inner electrodes and semiconductor patterns, which allows for adjustable threshold voltages and improved reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If MOS-FETs are scaled down to meet increasing demand for smaller pattern sizes, then device density and integration are improved, but operational properties and electrical characteristics deteriorate

Engineering Contradiction:
Improvepattern sizeVSAvoidoperational properties
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by differentiating the gate electrode structure into inner and outer regions with different material compositions. The inner gate electrode region contains aluminum or silicon at a first concentration, while the outer gate electrode region contains aluminum or silicon at a second concentration different from the first. This localized compositional variation optimizes electrical characteristics specifically in the critical inner region while maintaining overall device performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements parameter changes by varying the concentration of aluminum or silicon between the inner and outer gate electrode regions. By adjusting these compositional parameters, the patent optimizes the electrical and reliability characteristics of the scaled-down MOS-FET, addressing the deterioration caused by miniaturization.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If MOS-FETs are scaled down to reduce design rule, then manufacturing capability is improved, but electrical characteristics and reliability deteriorate

Engineering Contradiction:
Improvedesign ruleVSAvoidelectrical characteristics
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies local quality by creating distinct inner and outer gate electrode regions with different aluminum or silicon concentrations. This localized differentiation allows optimization of electrical characteristics in the critical inner region while maintaining manufacturability at reduced design rules.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses composite materials by combining different concentrations of aluminum or silicon within the gate electrode structure. The inner gate electrode region and outer gate electrode region form a composite structure that achieves both manufacturing feasibility at small scales and improved electrical characteristics.

Inventive Principle:
Principle #40Composite materials

3Reliability

If gate electrode composition is optimized for electrical performance, then device reliability is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical performanceVSAvoidgate electrode structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by differentiating only the aluminum or silicon concentration between inner and outer gate regions, rather than completely redesigning the gate structure. This targeted approach improves electrical performance while limiting the increase in overall device complexity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20230402523A1Semiconductor device
Publication Date: 2023.12.14 SAMSUNG ELECTRONICS CO LTD
  • US20230402523A1 patent drawing
  • US20230402523A1 patent drawing
  • US20230402523A1 patent drawing

AI summary

A semiconductor device includes first and second active patterns respectively provided on a first and second PMOSFET regions of a substrate, a first channel pattern on the first active pattern, the first channel pattern including first semiconductor patterns stacked and spaced apart from each other, a second channel pattern on the second active pattern, the second channel pattern including second semiconductor patterns stacked and spaced apart from each other, a first gate electrode on the first channel pattern, and a second gate electrode on the second channel pattern. A first concentration of aluminum (Al) or silicon (Si) in an inner gate electrode of the first gate electrode is different from a second concentration of aluminum (Al) or silicon (Si) in an inner gate electrode of the second gate electrode.