PMR Write Head Flux Loop Tuning for Area Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Perpendicular magnetic recording (PMR) write heads face challenges in maintaining high area density capability (ADC) while keeping adjacent track erasure (ATE) and bit error rate (BER) at acceptable levels, due to reduced magnetic flux in the trailing loop and increased stray fields in conventional double write shield (DWS) designs.
Innovation Solution
The PMR writer design enhances magnetic flux in the trailing return loop by increasing impedance in the leading return loop through modifications such as reducing the back gap connection (BGC) surface area, replacing magnetic sections with dielectric material, and thinning the return path layer, thereby maintaining sufficient flux in the leading loop to suppress stray fields and improve ADC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a double write shield (DWS) design is used to improve adjacent track erasure, then ATE is reduced, but magnetic flux in the trailing loop is reduced to 50% of non-DWS design, degrading hot seed response and area density capability
Solution Approach 1:
The patent modifies the magnetic flux distribution by changing the geometric parameters of the shield structures. Specifically, it adjusts the dimensions and positions of the leading and trailing shields to optimize flux distribution. This allows the trailing loop to receive sufficient flux while maintaining the ATE benefits of the DWS design.
Solution Approach 2:
The patent introduces asymmetric shield configurations where the leading and trailing shields have different dimensions and positions. This asymmetry allows unequal flux distribution between the two loops, enabling the trailing loop to have higher flux (improving ADC) while the leading loop maintains sufficient flux for ATE control.
2Productivity
If magnetic flux in the trailing loop is enhanced to improve area density capability, then ADC is improved, but sufficient magnetic flux in the leading loop is reduced, potentially increasing ATE and BER
Solution Approach 1:
The patent optimizes shield geometry parameters to control flux distribution. By adjusting shield dimensions, positions, and material properties, it achieves enhanced trailing loop flux for improved ADC while maintaining leading loop flux at levels sufficient to keep BER and ATE within acceptable ranges.
3Productivity
If the back gap connection surface area is reduced to increase impedance in the leading return loop, then magnetic flux in the trailing loop is enhanced, but the leading loop flux is reduced, requiring careful optimization to maintain ATE and BER levels
Solution Approach 1:
The patent systematically varies the BGC surface area and other geometric parameters to achieve optimal flux distribution. This parameter optimization allows the design to balance the competing requirements of high trailing loop flux (for ADC) and sufficient leading loop flux (for ATE and BER control).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved area density capability and reduced bit error rates, while maintaining acceptable ATE and BER levels, by enhancing magnetic flux in the trailing loop and retaining sufficient flux in the leading loop to suppress stray fields.
Implementation Method 1
coils that conduct a current and generate a magnetic flux in the main pole such that the magnetic flux exits through a write pole tip and enters a magnetic medium
Implementation Method 2
Magnetic flux is used to write a selected number of bits in the magnetic medium and typically returns to the main pole through two pathways including a trailing loop and a leading loop
Data Source
AI summary
A PMR writer is disclosed wherein magnetic flux return from a magnetic medium to a main pole is substantially greater through a trailing shield structure than through a leading return loop comprised of a leading shield, return path layer (RTP), and back gap connection (BGC). Magnetic impedance is increased between the RTP and main pole in the leading return loop by removing one or more layers in the BGC and replacing with dielectric material and non-magnetic metal to form a dielectric gap between the RTP and main pole. The non-magnetic metal may be Cu that is electrically isolated from coils within the write head. As a result, area density control and bit error rate are improved over a conventional dual write shield (DWS) structure comprising two flux return pathways. Moreover, adjacent track erasure is maintained at a level similar to a DWS design.