Precision Modulation Timer Integration for PLD Power Control
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Solution Overview
Problem
Programmable logic devices (PLDs) face limitations in handling high-voltage and high-current power applications due to the constraints of their internal I/O pins, requiring external discrete high-voltage power MOSFETs that increase cost and board space.
Innovation Solution
Integration of a precision modulation timer (PMT) block within a PLD, including a digital control block, counter, and pulse generator, configured via a programmable fabric and signal wrapper to provide programmable timing and pulse signals, enabling efficient power management for high-voltage applications without the need for external components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If external discrete high-voltage power MOSFETs are added to expand power application capabilities, then high-voltage and high-current handling capability is improved, but device complexity and board space increase
Solution Approach 1:
The patent merges the PLD with high-voltage power MOSFETs and associated control circuits (including precision modulation timer, comparator, and voltage reference) into a single integrated device. This combination eliminates the need for external discrete components while providing high-voltage power switching capability, directly resolving the contradiction between power handling capability and device complexity
Solution Approach 2:
The integrated device serves multiple functions: digital logic operations via the PLD, high-voltage power switching via the MOSFETs, precision timing via the PMT, voltage comparison via the comparator, and voltage reference generation. This multi-functionality allows a single device to replace multiple separate components, addressing both the power capability requirement and the complexity reduction goal
2Power
If external discrete high-voltage power MOSFETs are added to expand power application capabilities, then high-voltage and high-current handling capability is improved, but board space increases
Solution Approach 1:
The patent integrates the PLD, high-voltage power MOSFETs, precision modulation timer, comparator, and voltage reference into a single chip package. This merging of previously separate components into one integrated device dramatically reduces the board space required, as all components share the same physical substrate and require minimal external interconnections
3Power
If external discrete high-voltage power MOSFETs are added to expand power application capabilities, then high-voltage and high-current handling capability is improved, but cost increases
Solution Approach 1:
The patent combines multiple functions (PLD, power MOSFETs, PMT, comparator, voltage reference) into a single integrated circuit. This integration reduces the total component count, eliminates the need for multiple separate packages, and reduces assembly steps, all of which contribute to lower manufacturing costs despite the enhanced power capabilities
Solution Approach 2:
The multi-functional integrated device replaces multiple separate components that would each require individual procurement, packaging, and assembly. The single device approach leverages economies of scale in manufacturing and reduces inventory complexity, thereby reducing overall system cost while providing high-voltage power capability
Data Source
AI summary
A timer block includes: a digital control block including a mode selector and a register loading a time delay; a counter coupled to the register of the digital control block, wherein the counter loads a counter value corresponding to the time delay based on an operational mode selected by the mode selector and generates a digital output indicating the counter value that is decremented at each clock; and a pulse generator configured to generate a pulse signal based on the counter value of the counter. The timer block is integrated in a programmable logic device (PLD) including a programmable fabric and a signal wrapper that is configured to provide signals between the timer block and the programmable fabric. The operational mode of the timer block is programmably configured using the programmable fabric and the signal wrapper.