PMU Signal Protection Circuit for Clock Retention in Standby

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Solution Overview

Problem

Mobile devices face frequent recharging needs due to battery depletion, and existing solutions do not effectively preserve internal clock and register values during battery replacement, leading to inconvenience and potential loss of settings.

Innovation Solution

A power management unit with a signal protection circuit that transitions the device into a low-power standby mode, using a digitally controlled variable capacitor to gradually reduce capacitance and limit the rate of change of the gain control block input signal, thereby preserving clock signals during battery replacement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the device transitions to low-power standby mode during battery replacement, then power consumption is reduced and battery replacement becomes possible, but clock signals and register values may be lost

Engineering Contradiction:
Improvepower consumptionVSAvoidclock signal preservation
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The signal protection circuit is activated before the battery is removed to preserve clock signals. The circuit proactively prepares the protective mechanism in advance, ensuring that when the battery replacement occurs, the clock signals are already protected and will not be lost during the transition to standby mode and back.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The signal protection circuit acts as an intermediary between the clock output stage and the rest of the system. It receives the clock signal and provides a protected version, isolating the clock generation from the power state transitions and preventing signal loss during battery replacement.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If a high-performance crystal oscillator circuit is used, then clock signal accuracy is improved, but power consumption increases

Engineering Contradiction:
Improveclock signal accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The system dynamically switches between different oscillator performance modes. During battery replacement in standby mode, the signal protection circuit maintains clock signal integrity with minimal power consumption. When the device is fully operational, high-performance crystal oscillator circuits provide accurate clock signals. This dynamic adaptation allows the system to optimize the balance between clock accuracy and power consumption based on operational requirements.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables reliable and continuous clock functionality and retention of register values during battery replacement, allowing users to replace batteries without losing settings or clock signals, thus reducing the need for frequent recharging.

Implementation Method 1

limit a rate of change of a gain control loop input signal based on a time constant of the oscillator

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentEP2664976B1Power management unit including a signal protection circuit
Publication Date: 2018.05.16 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • EP2664976B1 patent drawingFigure 1
  • EP2664976B1 patent drawingFigure 2
  • EP2664976B1 patent drawingFigure 3

AI summary

The present application discloses various implementations of a power management unit (PMU) suitable for use in a mobile device. In one exemplary implementation, such a PMU includes a gain control block configured to control an oscillator coupled to the PMU. The gain control block is further configured to control a clock output stage of the PMU. The PMU also includes a signal protection circuit coupled to an input of the gain control block. The signal protection circuit is configured to preserve clock signals produced by the clock output stage during a transition to a standby mode.