Hardware PMU Clock Signal Switching for SoC Idle Power Reduction
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Solution Overview
Problem
Dynamic voltage and frequency scaling (DVFS) techniques, when applied during system idle states, inadvertently increase power consumption in electronic systems, particularly in System on Chip (SoC) devices, due to frequent CPU wake-ups for power management adjustments.
Innovation Solution
An application processor with a hardware power management unit (PMU) that supplies an oscillation clock signal instead of the standard clock signal when the system is idle, reducing power consumption by lowering the frequency and selectively turning off clock signal generators based on idle signals from CPUs and IPs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If DVFS is performed based on checking usage of target circuit during system operation, then power consumption is reduced to some extent, but when system is in idle state, DVFS itself adversely affects current consumption due to CPU periodically waking up
Solution Approach 1:
The patent extracts the power management function from the CPU and implements it in a dedicated hardware PMU. The PMU independently monitors idle signals and controls clock signal supply without requiring CPU intervention, thereby eliminating the need for CPU to periodically wake up and perform DVFS checks during idle states.
Solution Approach 2:
The hardware PMU acts as an intermediary between the CPU and the clock signal supply control circuit. It receives idle signals from the CPU, determines system idle state, and controls the switching between clock signals and oscillation clock signals, thereby preventing direct CPU involvement in idle-state power management.
2Productivity
If clock signal is supplied to CPU and IPs during idle state, then system performance is maintained, but power consumption increases unnecessarily
Solution Approach 1:
The system dynamically switches between different clock signal sources based on the idle state. During active operation, the high-frequency clock signal is supplied to maintain full system performance. During idle states, the hardware PMU detects the idle condition and switches to a low-frequency oscillation clock signal, thereby reducing power consumption while maintaining the ability to quickly resume full performance when needed.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal supplied to the system. By switching from the normal high-frequency clock signal to a low-frequency oscillation clock signal during idle states, the system reduces power consumption while maintaining operational capability. The hardware PMU controls this parameter change based on idle signal detection.
3Use of energy by moving object
If oscillation clock signal with lower frequency is supplied instead of clock signal during idle, then power consumption is reduced, but system performance may be affected
Solution Approach 1:
The hardware PMU periodically monitors idle signals from the CPU and IPs to determine whether the system is in an idle state. Based on this periodic detection, it switches between clock signal and oscillation clock signal supply, ensuring that full system performance is restored immediately when idle conditions no longer exist, thereby maintaining reliability while reducing power consumption during actual idle periods.
Data Source
AI summary
An application processor includes a central processing unit (CPU), intellectual properties (IPs), a hardware power management unit (PMU) configured to determine whether the application processor is in system idle based on a first idle signal output from the CPU and output control signals as a result of the determination, and a clock signal supply control circuit configured to change an output signal supplied to the CPU and the IPs from clock signals to an oscillation clock signal, based on the control signals. The oscillation clock signal has a frequency lower than that of the clock signals.