Multi-PMU Error Detection and Correction
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Solution Overview
Problem
Existing methods for detecting memory errors in computer systems are inadequate when errors from multiple physical memory units (PMUs) combine, even if no single PMU exceeds its error threshold, potentially leading to uncorrectable errors that require system halts.
Innovation Solution
A system and method that detect errors in data output from multiple PMUs, log occurrences, and flag symbols with the highest error counts, allowing evasive or corrective actions to prevent uncorrectable errors by using spare or redundant PMUs, even if individual error frequencies do not exceed predetermined thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error checking is performed only on individual PMUs against predetermined thresholds, then the detection method is simple and computationally efficient, but errors from multiple PMUs combining are not detected
Solution Approach 1:
The patent segments the error detection process into two distinct stages: (1) individual PMU error detection against predetermined thresholds, and (2) combined error detection by analyzing error patterns across multiple PMUs. This segmentation allows the system to maintain simple individual checks while adding a layer of综合分析 for combined errors, resolving the contradiction between detection reliability and mechanism complexity.
Solution Approach 2:
The patent introduces an intermediary analysis layer that processes error data from multiple PMUs before final error determination. This intermediary stage correlates errors across PMUs and identifies combined error patterns, enabling detection of multi-PMU errors without requiring complete redesign of the fundamental threshold-based detection mechanism.
2Reliability
If the error threshold is set low to detect more errors, then more errors are caught, but false positives increase and system performance degrades
Solution Approach 1:
The patent employs dynamic parameter adjustment by setting different error thresholds for different PMUs based on their individual error characteristics and usage patterns. This allows the system to optimize detection sensitivity for each PMU, catching more errors where appropriate while maintaining high performance where error rates are naturally low, thus resolving the contradiction between detection coverage and system performance.
3Reliability
If corrective action is taken immediately upon detecting errors from multiple PMUs, then uncorrectable errors are prevented, but system interruptions increase
Solution Approach 1:
The patent implements preliminary monitoring and correlation of errors from multiple PMUs before triggering corrective action. By tracking error patterns over time and identifying trends that suggest impending combined errors, the system can take preventive measures proactively, reducing the frequency of actual system interruptions while still preventing uncorrectable errors from occurring.
Data Source
AI summary
In a first aspect, a first method is provided for reducing memory errors. The first method includes the steps of (1) detecting at least one error in data output from a first physical memory unit (PMU) of a memory; (2) detecting at least one error in data output from a second PMU of the memory; and (3) setting a bit indicating respective data output from a plurality of PMUs includes errors. Numerous other aspects are provided.