PMU Startup Enable Circuit for Clock-Independent Power Sequencing
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Solution Overview
Problem
The startup of a power management unit (PMU) in integrated circuits (ICs) is challenging due to the initial external power supply starting at zero voltage, which is not sufficient to power digital logic, and the reliance on a clock that may not be properly working until the external power source is safe.
Innovation Solution
The proposed solution involves an apparatus with a delay circuit, a comparator, and a logic AND gate to determine when the supply voltage is stable and above a threshold, allowing for a safe and controlled startup of the PMU without relying on a clock. This apparatus includes analog and digital components that enable a self-timed startup sequence, ensuring the PMU powers the clock and other circuitry only after the external power supply is stable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PMU startup relies on a clock signal to sequence operations, then the startup can be synchronized and controlled, but the clock may not be properly working until the external power source is stable, causing startup failures
Solution Approach 1:
The patent implements preliminary voltage stability detection before enabling the clock and digital logic. The analog subcomponent detects whether the supply voltage is above a threshold before allowing the clock to start, ensuring that digital logic only operates when power is stable. This preliminary action prevents startup failures caused by unstable power without requiring complex control sequences.
Solution Approach 2:
The patent introduces an analog subcomponent as an intermediary between the power supply and the clock/digital logic. This intermediary detects voltage stability and controls the enable signal to the clock, acting as a mediator that ensures the clock only starts when power conditions are appropriate. This simplifies the overall control complexity by decoupling the power stability check from the clock control logic.
2Reliability
If the PMU startup waits for voltage stability detection, then digital logic can operate reliably, but the startup time increases due to the additional detection and delay requirements
Solution Approach 1:
The patent uses a delay circuit that rushes through the voltage stability detection process by implementing a fixed delay period after voltage threshold detection. Instead of continuously monitoring or waiting for extended periods, the system detects when voltage exceeds the threshold and immediately starts a predetermined delay sequence, allowing startup to proceed quickly once conditions are met while still ensuring stability.
3Productivity
If the PMU uses a self-timed startup sequence without a clock, then startup can begin immediately when voltage is stable, but the sequencing of operations becomes more complex
Solution Approach 1:
The patent implements periodic action through a structured startup sequence that progresses through defined stages: voltage threshold detection, fixed delay period, clock enablement, and digital logic activation. Each stage occurs in a predetermined periodic manner, providing clear sequencing without requiring complex real-time control logic. This periodic structure enables immediate startup when voltage is stable while maintaining operational reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a safe and asynchronous startup of the PMU, avoiding glitches caused by power spikes and drops, and ensuring the PMU can power digital components reliably once the supply voltage is stable.
Implementation Method 1
a delay circuit including an input terminal and an output terminal, the input terminal coupled of the delay circuit coupled to the input terminal
Implementation Method 2
a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal
Data Source
AI summary
An example apparatus includes an input terminal; an output terminal; a delay circuit including an input terminal and an output terminal, the input terminal coupled of the delay circuit coupled to the input terminal; a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal; and a logic AND gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic AND gate coupled to the output terminal of the comparator, the second input terminal of the logic AND gate coupled to the output terminal of the delay circuit, the third input terminal of the logic AND gate coupled to the input terminal, and the output terminal of the logic AND gate coupled to the output terminal.