P-N Column Layer Tapered Geometry for Semiconductor Stability
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Solution Overview
Problem
Existing methods for manufacturing semiconductor devices with P-N column layers struggle to consistently produce columns with high aspect ratios, leading to instability in both breakdown voltage and on-state resistance.
Innovation Solution
A semiconductor device and manufacturing method involving a P-N column layer with alternately arranged first and second conductivity type columns, each with a tapered shape and varying impurity concentrations, are used to achieve high aspect ratios and reduce crystal defects, thereby enhancing breakdown voltage and lowering on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If trench filling epitaxial layer is formed through anisotropic growth from bottom of each trench by LP-CVD with simultaneous silicon source gas and halide gas, then P-N column layer can be formed, but columns with high aspect ratios cannot be stably provided
Solution Approach 1:
The patent changes the etching gas flow rate parameter during the epitaxial growth process. Specifically, it sets the etching gas flow rate to be lower than the silicon source gas flow rate, which controls the anisotropic growth to achieve high aspect ratio columns with stable dimensions. This parameter optimization resolves the contradiction between achieving high aspect ratios and maintaining manufacturing stability.
Solution Approach 2:
The patent applies different gas flow rates at different stages of the epitaxial growth process. By controlling the silicon source gas and etching gas flow rates locally at each growth stage, it achieves uniform high aspect ratio columns throughout the P-N column layer, ensuring consistent breakdown voltage and on-state resistance across the entire structure.
2Strength
If columns with high aspect ratios are formed, then breakdown voltage increases, but manufacturing stability deteriorates
Solution Approach 1:
The patent optimizes the gas flow rate parameters to achieve the desired high aspect ratio columns that provide high breakdown voltage. By carefully controlling the ratio of silicon source gas to etching gas flow rates, it achieves the necessary column geometry for high breakdown voltage while maintaining stable manufacturing conditions.
Solution Approach 2:
The patent implements process monitoring and control to ensure consistent column formation. By monitoring the epitaxial growth process and adjusting gas flow rates accordingly, it maintains manufacturing stability while achieving the high aspect ratio columns necessary for high breakdown voltage performance.
3Ease of manufacture
If conventional LP-CVD method is used with halide gas as etching gas, then epitaxial growth can be achieved, but column shape control and stability are insufficient
Solution Approach 1:
The patent modifies the gas flow rate parameters in the conventional LP-CVD process. By setting the etching gas flow rate lower than the silicon source gas flow rate, it maintains the ease of manufacture of the LP-CVD process while achieving precise control over column shape and dimensions, producing stable high aspect ratio structures.
Solution Approach 2:
The patent applies localized control of gas flow rates during different stages of epitaxial growth. This allows the process to remain simple and manufacturable while achieving precise column shape control through stage-specific gas flow optimization, resolving the contradiction between ease of manufacture and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach allows for the reliable production of semiconductor devices with high breakdown voltage and low on-state resistance by ensuring the P-N column layer has columns with high aspect ratios and controlled impurity distributions, resulting in improved electrical properties.
Implementation Method 1
forming a first conductivity type epitaxial layer made of silicon on the first side of the substrate
Implementation Method 2
The halide gas functions as etching gas
Data Source
AI summary
A semiconductor device is provided, which includes a substrate; a P-N column layer disposed on the substrate; a second conductivity type epitaxial layer disposed on the P-N column layer. The P-N column layer includes first conductivity type columns and second conductivity type columns, which are alternately arranged. Each column has a tapered shape. A portion of the first conductivity type column located around the substrate has a smaller impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer. A portion of the second conductivity type column located around the substrate has a larger impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer.