Low-Parasitic Silicon Phase Modulator with PN Finger Waveguides
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed modulators in silicon-on-insulator (SOI) CMOS wafers suffer from parasitic capacitance due to etch transition features and doped regions, leading to performance limitations and increased power consumption.
Innovation Solution
The solution involves fabricating a low-parasitic silicon high-speed phase modulator by reducing the area of p-doped and n-doped regions and removing etch transition features, integrating the modulator in a Mach-Zehnder interferometer, and forming staggered fingers for contact formation, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-speed modulators are implemented in SOI CMOS wafers, then modulation functionality is achieved, but parasitic capacitance increases due to etch transition features and doped regions
Solution Approach 1:
The patent removes etch transition features from the modulator structure and extracts only the necessary doped regions (forming finger-like contacts) while eliminating unnecessary doped areas. This extraction of harmful elements directly reduces parasitic capacitance while preserving the essential modulation functionality through the remaining functional doped regions.
Solution Approach 2:
The doped regions are segmented into finger-like contacts distributed along the waveguide length, rather than forming continuous large-area regions. This segmentation reduces the total area of doped regions in contact with the substrate, thereby reducing parasitic capacitance while maintaining effective carrier depletion for phase modulation.
2Loss of energy
If doped regions are reduced in area to lower parasitic capacitance, then power consumption decreases, but modulation efficiency may be compromised
Solution Approach 1:
The patent uses high-speed carrier depletion through reverse-biased PN junctions to dynamically modulate the refractive index, rather than relying on static doped regions. This dynamic mechanism allows efficient modulation with minimal doped area, as the effect is achieved through carrier removal rather than through large volumes of doped material, thereby reducing both power consumption and parasitic capacitance.
Solution Approach 2:
The doped regions are concentrated locally at the waveguide-core interfaces where they are most effective for carrier depletion, rather than being distributed uniformly. This local concentration maximizes modulation efficiency per unit area of doped region, allowing reduced total doped area while maintaining modulation performance.
3Object-generated harmful factors
If etch transition features are removed, then parasitic capacitance is reduced, but manufacturing complexity may increase
Solution Approach 1:
The patent applies a single deep etch process that extends fully through the silicon layer to the oxide substrate, eliminating the need for multiple etch transitions. While this creates a more aggressive etch condition, it simplifies the overall fabrication by removing the complexity of managing multiple etch depth transitions, and the resulting uniform deep etch actually reduces parasitic capacitance by eliminating transition-region artifacts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces parasitic capacitance, enhancing modulator performance and power efficiency while maintaining high bandwidth, effectively addressing the limitations of conventional high-speed modulators.
Implementation Method 1
a PN junction waveguide formed in a silicon layer... p-doped and n-doped regions on opposite sides along a length of the PN junction waveguide
Implementation Method 2
A parasitic capacitance of the optical phase modulator may be reduced by the removing of portions of the p-doped and n-doped regions
Implementation Method 3
a silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) wafer... oxide layer on a silicon substrate
Data Source
AI summary
Methods and systems for a low-parasitic silicon high-speed phase modulator are disclosed and may include in an optical phase modulator that comprises a PN junction waveguide formed in a silicon layer, wherein the silicon layer may be on an oxide layer and the oxide layer may be on a silicon substrate. The PN junction waveguide may have fingers of p-doped and n-doped regions on opposite sides along a length of the PN junction waveguide. Contacts may be formed on the fingers of p-doped and n-doped regions. The fingers of p-doped and n-doped regions may be arranged symmetrically about the PN junction waveguide or staggered along the length of the PN junction waveguide. Etch transition features may be removed along the p-doped and n-doped regions.