PN Floating Gate Non-Volatile Storage Elements
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Solution Overview
Problem
As memory arrays scale, data retention and stress-induced leakage currents (SILC) become significant issues due to wider threshold voltage ranges and limitations in reducing tunnel oxide thickness, affecting the margin between voltage distributions and programming efficiency.
Innovation Solution
Implementing a P-N floating gate structure in non-volatile storage devices, where a P− region is near the tunnel oxide and an N+ region is near the control gate, with a thin barrier to prevent impurity diffusion, enhancing data retention and coupling ratio while maintaining programming speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the tunnel oxide thickness is reduced to continue scaling, then memory density increases, but data retention deteriorates and stress-induced leakage currents increase
Solution Approach 1:
The floating gate is divided into two regions with different doping types: a P-type region adjacent to the tunnel oxide and an N-type region adjacent to the control gate. This local differentiation of properties allows the P-region to provide high electron barrier for data retention at the tunnel oxide interface while the N-region maintains good coupling ratio with the control gate, resolving the contradiction between scaling and reliability.
Solution Approach 2:
The floating gate uses a composite doping structure combining P-type and N-type semiconductor regions within the same floating gate body. This composite approach leverages the complementary properties of opposite doping types to simultaneously achieve both data retention and programming efficiency that cannot be obtained with a single doping type.
2Adaptability or versatility
If the threshold voltage ranges are widened to accommodate scaling, then more states can be stored, but the margin between voltage distributions decreases
Solution Approach 1:
The P-type region is specifically positioned at the tunnel oxide interface where it provides superior electron barrier properties, enabling better data retention and sharper threshold voltage distribution. This local quality enhancement at the critical interface allows for wider voltage ranges to be used without sacrificing the margin between distributions.
3Reliability
If a P-type floating gate is used to improve data retention, then electron barrier increases, but coupling ratio with control gate deteriorates
Solution Approach 1:
The floating gate employs different doping types at different locations: P-type at the tunnel oxide interface for high electron barrier and data retention, and N-type at the control gate interface for high coupling ratio. This spatial differentiation of doping properties resolves the contradiction between retention and coupling.
Solution Approach 2:
The floating gate is segmented into functionally distinct regions: a P-type segment adjacent to the tunnel oxide for retention and an N-type segment adjacent to the control gate for coupling. This segmentation allows each region to optimize its local function without compromising the other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves data retention margins, allows for potential reduction in tunnel oxide thickness, and maintains efficient programming and erasing processes, addressing the challenges of scaling and SILC.
Implementation Method 1
a thin barrier to prevent impurity diffusion
Data Source
AI summary
Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.