PN Junction Structure in BSPDN Chips With Backside Space Constraints
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Solution Overview
Problem
The back side thinning process for semiconductor devices often results in insufficient space for forming passive devices or PN junction devices, leading to routing congestion and limitations in power delivery networks.
Innovation Solution
Incorporating a back side power delivery network (BSPDN) structure with integrated passive devices or PN junction devices, where transistors are formed in one layer and the BSPDN structure is in another layer below, connecting field-effect transistors to a voltage source, and forming PN junction devices either above or alongside the BSPDN structure to alleviate space constraints and routing issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the substrate is removed through back side thinning to provide BSPDN structure, then routing complexity at BEOL is reduced, but insufficient space remains for forming passive devices or PN junction devices
Solution Approach 1:
The patent utilizes the back side of the semiconductor device as an additional dimension for forming the BSPDN structure and passive devices. By moving power delivery networks and passive devices to the back side, the patent resolves routing complexity at the front BEOL while simultaneously providing sufficient space for passive devices through the vertically stacked configuration.
Solution Approach 2:
The patent segments the semiconductor device into distinct functional layers: the front side contains active transistor circuits, while the back side contains the BSPDN structure with passive devices and PN junction devices. This segmentation allows independent optimization of routing on the front side and space utilization on the back side, resolving both the routing complexity and space constraints simultaneously.
2Adaptability or versatility
If more passive devices and PN junction devices are integrated, then device functionality is enhanced, but routing congestion increases at BEOL
Solution Approach 1:
The patent resolves routing congestion by relocating passive devices and PN junction devices to the back side, creating a three-dimensional layout that separates power delivery routing from signal routing. This dimensional separation allows enhanced device functionality with multiple passive devices without increasing front-side BEOL routing congestion.
Data Source
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Figure 4A~4B
AI summary
Provided is a semiconductor device that includes: at least one field-effect transistor and at least one PN junction device (100c) at a lateral side of the at least one field-effect transistor in a 1st layer (TL); and at least one back side power delivery network, BSPDN, structure in a 2nd layer (BL) below the 1st layer, wherein the at least one BSPDN structure is configured to connect the at least one field-effect transistor to a voltage source.