PN-Junction CMOS Transistor Pair for Abrupt Low-Power Switching
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Solution Overview
Problem
Current CMOS technologies, such as FDSOI transistors, face limitations in low-power applications and protection against electrostatic discharges, particularly in achieving abrupt switching and high performance.
Innovation Solution
A microelectronic device comprising n-MOS and p-MOS field effect transistors with a PN junction, where the N-doped and P-doped zones form a PN junction, allowing for abrupt switching and low power consumption, and a method of controlling the device using specific voltage applications to switch between passing and blocked configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If FDSOI transistor structure is used, then current leaks are avoided and low-power applications are enabled, but abrupt switching performance is limited
Solution Approach 1:
The patent combines an n-MOS transistor and a p-MOS transistor into a single integrated device structure, where the n-MOS provides low-power operation and the p-MOS enables abrupt switching. The two transistor types are merged such that they share common structural elements (substrate, gate regions, insulating layer) while maintaining distinct doped zones that form a PN junction, achieving both low current leak and high switching speed performance
Solution Approach 2:
The patent incorporates a PN junction formed by N-doped and P-doped zones that are pre-configured to enable abrupt switching behavior. The doped zones are strategically positioned and doped beforehand to create the necessary junction characteristics that facilitate rapid state transitions, allowing the device to achieve abrupt switching without requiring additional external components or complex control circuits
2Ease of manufacture
If conventional transistor structures are used, then manufacturing simplicity is maintained, but performance for high slope devices is insufficient
Solution Approach 1:
The patent segments the transistor structure into distinct functional zones: n-doped zones for the n-MOS transistor, p-doped zones for the p-MOS transistor, gate regions, and insulating layers. This segmentation allows each zone to be optimized for its specific function while maintaining overall structural simplicity. The clear spatial separation of doped regions facilitates straightforward manufacturing processes while achieving the complex performance characteristics of abrupt switching and low-power operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves high performance with low power consumption, enabling efficient switching and improved energy efficiency, suitable for low-power electronic systems and applications requiring rapid state transitions.
Implementation Method 1
The device also has the particularity that the second N-doped zone and the second P-doped zone form a PN junction
Data Source
Figure 1~2A
Figure 2B~3A
Figure 3B~3C
AI summary
The invention relates to a microelectronic device (1) comprising an n-MOS field-effect transistor (100), a first N-doped region (110), one of the drain and one of the source of the n-MOS transistor, and a second N-doped region (120), the other of the drain and one of the source of the n-MOS transistor. The device according to the invention further comprises a p-MOS field-effect transistor (200), a first P-doped region (210), one of the drain and one of the source of the p-MOS transistor, a second P-doped region (220), the other of the drain and one of the source of the p-MOS transistor, a dielectric layer (300) in contact with the doped regions, and a back gate (400). The n-MOS transistor and the p-MOS transistor are separated by a PN junction (1000).