Semiconductor P-N Junction Isolation via Bias Layer

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Solution Overview

Problem

The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in achieving effective P-N junction isolation structures.

Innovation Solution

A semiconductor device design featuring a substrate with a first well layer, bottom conductive layers, insulating layers, and conductive lines configured as programmable units, where the bottom conductive layers have a second electrical type opposite to the first well layer, and a bias layer is used to apply biased voltage for electrical isolation, allowing for more functional elements and improved uniformity of insulating layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional isolation structures are used in scaled-down semiconductor devices, then manufacturing complexity increases, but electrical isolation effectiveness deteriorates

Engineering Contradiction:

Improveelectrical isolation effectivenessVSAvoidisolation structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the isolation function from traditional complex isolation structures and implements it through a simplified P-N junction-based isolation mechanism. The isolation-mask layer encloses the bottom conductive layers, and the bias layer applies voltage to create depletion regions that provide electrical isolation, eliminating the need for complex multi-layer isolation structures.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the electrical parameters by applying biased voltage to the bias layer, which has a third electrical type different from both the first well layer and bottom conductive layers. This voltage application creates depletion regions that dynamically control electrical isolation, replacing static complex structural isolation with dynamic parameter-based isolation.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If substrate area is reduced for scaling, then device density improves, but available area for functional elements decreases

Engineering Contradiction:

Improvedevice densityVSAvoidsubstrate area for functional elements

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent merges the isolation function with the P-N junction structure itself. The isolation-mask layer and bias layer are integrated into the existing P-N junction fabrication process, combining multiple functions into a unified structure that doesn't require additional dedicated isolation area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The P-N junction structure serves multiple functions: it provides the primary device functionality while simultaneously providing electrical isolation through the bias layer. The bottom conductive layers serve both as electrical contacts and as part of the isolation structure when enclosed by the isolation-mask layer, maximizing substrate utilization.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Length of moving object

If insulating layer thickness is reduced for scaling, then device size decreases, but uniformity and thickness consistency deteriorate

Engineering Contradiction:

Improveinsulating layer thicknessVSAvoidinsulating layer uniformity

Core Design Contradiction:

Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent introduces the bias layer as an intermediary that applies electrical control to the isolation mechanism. This allows the system to achieve effective electrical isolation without relying solely on physical insulating layer thickness, thereby maintaining uniformity and thickness consistency while enabling device scaling.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enables efficient electrical isolation of bottom conductive layers, conserves substrate area for additional functional elements, and enhances the reliability of programming by improving the uniformity and thickness consistency of insulating layers.

Implementation Method 1

a bias layer positioned in the first well layer and spaced apart from the bottom conductive layer... efficient electrical isolation of bottom conductive layers

Methodology Applied

Scientific EffectP-N junction depletion region: Electric Field

Data Source

PatentUS11676998B2Method for fabricating semiconductor device with P-N junction isolation structure

Publication Date: 2023.06.13 NAN YA TECH

AI summary

The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first well layer in the substrate and having a first electrical type, forming an isolation-mask layer on the first well layer, forming mask openings along the isolation-mask layer to expose portions of the first well layer, forming bottom conductive layers in the portions of the first well layer, forming a bias layer in the first well layer and spaced apart from the bottom conductive layers, forming first insulating layers on the bottom conductive layers, forming first conductive lines on the first insulating layers and parallel to each other. The bottom conductive layers have a second electrical type opposite to the first electrical type. The bottom conductive layers, the first insulating layers, the first conductive lines together configure programmable units.