PN Superjunction Planarization via Etch-Back
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Solution Overview
Problem
The conventional fabrication process of PN superjunctions requires dedicated CMP equipment for planarization, leading to complex process control and increased production costs, which are not compatible with conventional semiconductor manufacturing processes.
Innovation Solution
A method involving the formation of an N-type epitaxial layer, sequential dielectric layers, deep trench formation, complete filling with P-type epitaxial material, a surface filling layer using a flowable dielectric, and a plasma etch-back process to planarize the epitaxial layer, replacing the need for CMP equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used for planarization, then surface flatness is improved, but process complexity and production cost increase
Solution Approach 1:
The patent extracts the planarization function from the CMP process and implements it through a self-aligned etch-back mechanism. The sacrificial dielectric layer is removed after epitaxial growth, causing the overgrown epitaxial layer to automatically return to the original trench depth, achieving planarization without CMP equipment.
Solution Approach 2:
The patent makes the epitaxial growth process serve multiple functions: filling the deep trenches with P-type material and simultaneously planarizing the surface. By controlling the epitaxial overgrowth and subsequent etch-back, the same process achieves both trench filling and surface flatness, eliminating the need for dedicated CMP equipment.
2Manufacturing precision
If CMP process is used for planarization, then surface flatness is improved, but production cost increases
Solution Approach 1:
The patent removes the dependency on expensive CMP equipment by extracting the planarization function and implementing it through standard epitaxial growth and etch-back processes that are already part of the semiconductor fabrication toolkit.
Solution Approach 2:
The patent introduces a sacrificial dielectric layer that is temporarily added and then removed to enable the planarization mechanism. This disposable layer facilitates the self-aligned etch-back process, achieving cost-effective planarization without requiring expensive CMP equipment.
3Manufacturing precision
If CMP process is used for planarization, then surface flatness is improved, but process control difficulty increases
Solution Approach 1:
The patent implements a self-feedback mechanism where the epitaxial layer overgrows the trench and then etches back to the original level. The etch-back process automatically stops when the sacrificial dielectric layer is removed, providing inherent process control without requiring complex CMP parameter management.
Solution Approach 2:
The epitaxial growth process automatically planarizes the surface through self-aligned overgrowth and etch-back. The process is self-regulating, as the etch-back stops precisely when the sacrificial layer is removed, eliminating the need for external process control mechanisms required by CMP.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process, enhances efficiency, reduces production costs, and avoids the instability issues associated with CMP planarization, allowing for compatible integration with existing semiconductor fabrication processes.
Implementation Method 1
an etching step for etching back the surface filling layer and the epitaxial material to the interface of the first dielectric layer and the epitaxial layer
Implementation Method 2
the above mentioned filling dielectric is a flowable dielectric
Data Source
Figure 1
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AI summary
The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a depostion step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.