PNM Cache Processing for Low-Latency RAID Strip Access

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Solution Overview

Problem

The existing RAID technology is inefficient due to long data access times from the CPU memory, leading to high CPU utilization and limited resources, especially in high-performance storage scenarios.

Innovation Solution

Implementing a Processing Near Memory (PNM) device with a PNM processor and cache memory to directly pull strip data from the cache memory for processing, reducing the distance and time required for data access, and offloading intensive computations from the CPU.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is stored in CPU memory and processed by CPU, then data storage capacity is sufficient, but data access time is long and processing efficiency is low

Engineering Contradiction:

Improvedata access speedVSAvoiddata access time

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent introduces a PNM device as an intermediary component between the CPU and storage devices. This PNM device includes a cache memory and processing units that can independently perform RAID operations, acting as a mediator that reduces the distance and time for data access while enabling parallel processing operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the data processing function by separating RAID processing from the CPU. The PNM device is divided into multiple processing units that can independently handle different RAID operations (such as parity calculation, data reconstruction) while the CPU focuses on higher-level tasks, thereby improving overall processing efficiency.

Inventive Principle:

Principle #1Segmentation

2Productivity

If CPU performs RAID operations, then data processing is centralized, but CPU utilization is high and resources are limited

Engineering Contradiction:

Improvedata processing efficiencyVSAvoidCPU resources

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent extracts the RAID processing function from the CPU and relocates it to the PNM device. This extraction allows the CPU to focus on other tasks while the PNM device handles intensive RAID operations independently, thereby improving data processing efficiency without overloading CPU resources.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The PNM device is designed to autonomously perform RAID operations such as parity calculation, data reconstruction, and cache management without requiring continuous CPU intervention. This self-service capability reduces CPU occupancy and enables parallel processing, thereby improving overall productivity.

Inventive Principle:

Principle #25Self-service

3Reliability

If data is accessed from CPU memory, then data availability is ensured, but access latency is high

Engineering Contradiction:

Improvedata availabilityVSAvoidaccess latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements a cache memory in the PNM device that pre-loads and stores frequently accessed data and strip data. This preliminary action ensures that data is readily available when needed, reducing access latency while maintaining data availability through the cache hierarchy.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20260086947A1Data processing method and device thereof

Publication Date: 2026.03.26 SAMSUNG ELECTRONICS CO LTD

AI summary

The present disclosure includes a data processing method. The method is executed by one or more processors of a processing near memory (PNM) device, where the PNM device comprises a PNM processor and a cache memory. The method includes pulling, from a memory of a central processing unit of a host associated with the PNM device, strip data related to target data processing and storing the strip data in the cache memory; and pulling, from the cache memory, the strip data strip by strip, and performing the target data processing.