Pseudo Non-Maskable Interrupt Handling in ARM64 Processors
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Solution Overview
Problem
The transition from x86 processors to ARM64 processors poses difficulties for operating systems due to the absence of non-maskable interrupts (NMIs) in the ARM64 core ISA and Generic Interrupt Controller (GIC), which are essential for maintaining system functions like TLB maintenance and performance monitor counter servicing.
Innovation Solution
Implementing a pseudo non-maskable interrupt (PNMI) mechanism that distinguishes between NMIs and regular interrupts, allowing the operating system to emulate NMI behavior by using a priority interrupt controller, enabling or disabling interrupts based on a mask flag, and handling PNMI and regular interrupts accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ARM64 processor with GIC is used instead of x86 processor, then device compatibility and mobile device support are improved, but the ability to handle non-maskable interrupts (NMI) is lost
Solution Approach 1:
The patent introduces a priority interrupt controller as an intermediary layer between the GIC and the processor core. This controller intercepts interrupt requests before they reach the GIC, identifies PNMI requests based on priority levels, and routes them appropriately. The intermediary enables NMI-like functionality on ARM64 by mediating the interrupt handling process without requiring changes to the underlying processor architecture.
Solution Approach 2:
The patent changes the parameter used to identify high-priority interrupts by utilizing the priority field in the interrupt request structure. By interpreting specific priority values as indicating PNMI requests, the system repurposes existing GIC parameters to achieve NMI behavior. This parameter-based differentiation allows the system to distinguish between regular interrupts and pseudo-NMIs without adding new hardware signals.
2Reliability
If a priority interrupt controller is implemented to enable PNMI, then NMI functionality is restored, but device complexity increases
Solution Approach 1:
The priority interrupt controller is designed to handle multiple types of interrupts through a unified interface. It simultaneously manages regular interrupts, pseudo-NMIs, and high-priority interrupts using the same hardware structure and processing logic. This multi-functional design avoids the need for separate dedicated NMI hardware, reducing overall system complexity while maintaining full interrupt handling capabilities.
Solution Approach 2:
The system implements self-service by having the operating system software configure the priority interrupt controller to automatically route interrupts based on their priority levels. The controller autonomously identifies PNMI requests and directs them to appropriate handlers without requiring additional hardware assistance or complex control logic. This self-configuring approach simplifies the hardware design while maintaining sophisticated interrupt management.
3Stability of the object's composition
If interrupts are disabled during regular interrupt handling, then interrupt nesting is prevented, but PNMI delivery is blocked
Solution Approach 1:
The patent applies local quality by creating different interrupt handling contexts for different interrupt types. When a regular interrupt is being serviced, the system maintains interrupt disabling for regular interrupts to ensure stability, but simultaneously enables or allows pseudo-NMIs to pass through based on their higher priority designation. This localized differentiation in interrupt handling permissions allows the system to maintain stability for routine operations while remaining responsive to critical events.
Solution Approach 2:
The system performs preliminary action by pre-configuring the priority interrupt controller to recognize and prioritize PNMI requests before they reach the interrupt handling code. The controller is set up in advance to identify high-priority interrupts and ensure they can interrupt regular interrupt service routines. This preliminary configuration ensures that when regular interrupts are masked, PNMI delivery paths remain open and functional.
Data Source
AI summary
A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a PNMI, executing a PNMI interrupt handler. If the received interrupt is a regular interrupt, the method further comprises reading a mask flag that indicates whether regular interrupts are enabled in an interrupt controller and further: if the mask flag indicates that regular interrupts are enabled, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing, a regular interrupt handler, and disabling interrupts in the processor; and if the mask flag indicates that regular interrupts are disabled, saving the interrupt vector for subsequent handling.