P-Channel Device NBTI Reliability via Exponential Defect Distribution
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Solution Overview
Problem
Negative bias temperature instability (NBTI) is a significant reliability concern for submicron CMOS technologies, particularly in PMOS transistors, leading to degradation of device parameters like threshold voltage and transconductance, especially in sub-1 nm effective oxide thickness (EOT) devices, where increased oxide electric fields exacerbate the issue, limiting operational lifetimes.
Innovation Solution
A P-channel semiconductor device with a gate dielectric layer having an exponentially-shaped distribution of defect levels, where the inversion carrier injection occurs close to the center of the bandgap, reducing interaction between carriers and defect levels, achieved by optimizing the thickness and composition of the P-channel layer and capping layer, such as increasing the SiGe layer thickness and Ge content, and decreasing the capping layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the effective oxide thickness (EOT) is reduced to improve MOSFET performance, then device performance is improved, but NBTI reliability deteriorates due to increased oxide electric field
Solution Approach 1:
The patent applies local quality by creating a non-uniform defect distribution within the gate dielectric layer. Instead of uniform defects, the defect concentration varies spatially, with higher concentration near the semiconductor interface and lower concentration toward the gate electrode. This localized defect engineering allows the device to maintain lower overall defect interaction while preserving the thin EOT structure needed for high performance.
Solution Approach 2:
The patent changes the energy distribution parameter of defects in the gate dielectric from a uniform distribution to an exponentially-shaped distribution. This parameter change in defect energy levels causes inversion carriers to be injected closer to the center of the bandgap rather than being trapped at band-edge defects, thereby reducing NBTI degradation while maintaining sub-1 nm EOT for high device performance.
2Speed
If inversion carrier injection occurs at band-edge defect levels, then carrier transport is facilitated, but interaction with high defect concentration regions increases NBTI degradation
Solution Approach 1:
The patent introduces an intermediary mechanism where the exponentially-shaped defect energy distribution acts as a mediator between carriers and defects. Instead of direct interaction at band-edge defect levels, carriers interact with defects through this engineered energy distribution profile, which shifts the effective interaction point toward the bandgap center where defect concentration is lower, reducing NBTI while maintaining transport.
3Ease of operation
If the gate dielectric defect energy level is coupled with majority carriers, then device operation is enabled, but NBTI degradation occurs due to hole trapping
Solution Approach 1:
The patent inverts the conventional approach by instead of coupling defect levels with majority carriers at band edges, it engineers the defect energy distribution to cause carrier injection closer to the bandgap center. This inversion of the interaction mechanism enables device operation while avoiding the harmful hole trapping that occurs at band-edge defect levels, thereby improving NBTI reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances NBTI reliability, allowing for increased operating overdrive voltages while guaranteeing a 10-year device lifetime, even in sub-1 nm EOT devices, by decoupling the gate dielectric defect energy level from majority carriers and reducing interaction with high defect concentration regions.
Implementation Method 1
there being an energy bandgap between the conduction band and the valence band
Implementation Method 2
The gate dielectric layer has an exponentially-shaped distribution of defect levels E(defect) in its energy bandgap, the exponentially-shaped distribution of defect levels having a lower concentration of defect levels at the centre of the bandgap and a higher concentration of defect levels at the edges of the bandgap
Implementation Method 3
As inversion carrier injection into the distribution of defect levels takes place from the P-channel layer into the gate dielectric layer
Implementation Method 4
selecting at least one parameter of the P-channel semiconductor device such that the inversion carrier injection into the distribution of defect levels occurs as close as possible to the centre of the bandgap
Data Source
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AI summary
The present invention provides a method for forming a semiconductor device comprising a semiconductor P-channel layer and a control electrode on the semiconductor P-channel layer comprising at least a gate dielectric layer, the gate dielectric layer having an exponentially decreasing density of defect levels Et in as function of energy from the band edges of the adjacent layer (being the semiconductor P-channel layer 12 or optionally the capping layer 13) toward the centre of the bandgap of this layer. The method comprises selecting at least one parameter of the P-channel semiconductor device such that the inversion carrier injection into the distribution of defect levels does deviate from the energy level at the centre of the bandgap of a layer adjacent the gate dielectric layer at the same side of the gate dielectric layer as the P-channel layer, with a value not more than 49%, such as not more than 40%, for example not more than 20%, not more than 10%, even not more than 5% of that bandgap in eV. This allows reducing NBTI.