PNP-Triggered SCR Latch-Up Prevention via Current Threshold
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Solution Overview
Problem
Traditional SCR-based ESD protection devices suffer from latch-up issues, particularly at high voltage processes, due to parasitic PNP and NPN structures, leading to disruptions or destruction of circuits during ESD events, and existing solutions to increase holding voltage consume more device and chip area.
Innovation Solution
A latch-up robust PNP-triggered SCR-based device is designed with a PNP region and SCR region in a substrate, where specific n-well and P+ regions are coupled to power and ground rails, creating ESD current paths that prevent latch mode until a pre-designated trigger threshold is satisfied, set at over 100 mA, thereby avoiding latch-up without increasing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SCR-based ESD protection devices are used, then compact size and robust ESD performance are achieved, but latch-up issues occur during high voltage ESD events
Solution Approach 1:
A PNP region is introduced as an intermediary component between the SCR region and the substrate. This PNP region acts as a mediator that controls the triggering behavior of the SCR, ensuring that the SCR only activates when the trigger current exceeds a predetermined threshold, thereby preventing unwanted latch-up while maintaining ESD protection capability
Solution Approach 2:
The patent modifies the trigger characteristics of the SCR by changing the triggering mechanism from voltage-based to current-based through the PNP region. The PNP region is designed with specific parameters (emitter area, doping concentration) that establish a predetermined trigger current threshold, transforming the device behavior to be latch-up robust while maintaining compact size
2Reliability
If p-n junction space is increased or SCR is cascaded to increase holding voltage, then latch-up issues are reduced, but device and chip area substantially increases
Solution Approach 1:
The PNP region is merged with the SCR structure in a compact integrated layout. The PNP emitter is positioned adjacent to the SCR cathode, and the PNP collector is connected to the SCR anode, creating a compact configuration that achieves latch-up robustness without requiring increased device area
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional integration of the PNP region with the SCR structure. By arranging components in multiple layers and utilizing vertical space, the design achieves the required electrical characteristics without expanding the planar device footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents latch-up in SCR-based devices during ESD events with a high trigger current threshold, ensuring robust ESD performance and minimal impact on device size and chip area, suitable for various semiconductor applications.
Implementation Method 1
If there is enough charge to maintain parasitic PNP and NPN structures, latch-up path 121 may occur
Implementation Method 2
an ESD event (e.g., from I/O pad 119 to ground rail 113) may induce reverse breakdown with respect to n-well region 105 and substrate 101
Data Source
AI summary
An approach for providing a latch-up robust PNP-triggered SCR-based device is disclosed. Embodiments include providing a silicon control rectifier (SCR) region; providing a PNP region having a first n-well region proximate the SCR region, a first N+ region and a first P+ region in the first n-well region, and a second P+ region between the SCR region and the first n-well region; coupling the first N+ region and the first P+ region to a power rail; and coupling the second P+ region to a ground rail.