Physically Obfuscated Circuit Bit Stability via Asymmetry
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Solution Overview
Problem
Current physically obfuscated circuits (POCs) face limitations in bit stability and statistical quality, making them vulnerable to attacks and requiring expensive error correction measures, especially in silicon Arbiter POCs which suffer from asymmetric wirings and poor delay skews due to process variations.
Innovation Solution
The implementation of TIE cells with p-channel and n-channel field effect transistors, utilizing deep sub-threshold relaxation processes to generate POC values, which are highly sensitive to manufacturing variations, allowing for stable-bit-marking and pre-selection of bits, thereby enhancing bit stability and reproducibility without the need for error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon Arbiter POCs are implemented, then POC values can be generated, but bit stability and statistical quality deteriorate due to asymmetric wirings and process variations
Solution Approach 1:
The patent intentionally introduces controlled asymmetry through dummy transistors and dummy wiring to compensate for manufacturing variations. By adding asymmetric compensation elements, the circuit achieves symmetric delay behavior despite inherent process variations, thereby improving bit stability without requiring perfect manufacturing precision.
Solution Approach 2:
The patent modifies circuit parameters by adding dummy transistors with specific dimensions (e.g., width and length ratios) to adjust delay characteristics. This parameter adjustment compensates for process variations and achieves consistent delay skew across different manufacturing conditions, resolving the contradiction between reliability and manufacturing precision.
2Reliability
If error correction measures are implemented to improve bit stability, then reliability improves, but device complexity and cost increase
Solution Approach 1:
The patent performs preliminary action by pre-compensating for delays using dummy transistors and dummy wiring before the actual POC value generation. This preliminary delay compensation ensures that subsequent measurements are already corrected for manufacturing variations, eliminating the need for complex error correction circuitry and reducing overall device complexity.
Solution Approach 2:
The patent introduces dummy transistors and dummy wiring as intermediary elements that mediate between the inherent manufacturing variations and the POC value generation process. These intermediaries absorb and compensate for variations, providing stable delay characteristics without requiring complex error correction mechanisms.
3Reliability
If deep sub-threshold relaxation processes are utilized, then sensitivity to manufacturing variations increases, but bit stability improves through stable-bit-marking
Solution Approach 1:
The patent converts the harmful effect of manufacturing variations into a beneficial feature by using stable-bit-marking. The deep sub-threshold relaxation processes amplify sensitivity to variations, and this sensitivity is harnessed to create uniquely identifiable stable bits that can be reliably used for POC value generation, turning manufacturing imprecision into a security advantage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a secure and cost-efficient POC solution with significantly improved resistance to physical attacks and high reproducibility, eliminating the need for error correction, ensuring stable and secure secret-key generation for cryptographic applications.
Implementation Method 1
utilizing deep sub-threshold relaxation processes to generate POC values
Data Source
AI summary
A physically obfuscated circuit (POC) circuit including a plurality of subcircuits, each comprising at least one p-channel field effect transistor (FET) and at least one n-channel FET, connected such that the at least one n-channel FET, if supplied with an upper supply potential at its gate, supplies a lower supply potential to the gate of the at least one p-channel FET and the at least one p-channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n-channel FET.