Pocket-Integrated FeRAM Capacitors for Precise Thickness Control
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Solution Overview
Problem
Integration of ferroelectric random-access memory (FeRAM) devices on the same plane as interconnects of logic devices is challenging due to the difficulty in etching materials with varying thicknesses and height constraints, which complicates the formation of high-density arrays.
Innovation Solution
A pocket integration process is employed, utilizing non-lead-based perovskite materials and a multistep subtractive patterning method to form ferroelectric capacitors with a tuned thickness, incorporating an insulator layer in the logic region and conductive interconnects in the memory region, enabling precise thickness control and reducing electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional etching methods are used for FeRAM devices with varying thicknesses, then the etching process becomes difficult and complex, but the manufacturing precision and device density are compromised
Solution Approach 1:
The patent segments the FeRAM device structure by introducing a recessed region with a first thickness and non-recessed regions with a second thickness. This segmentation allows different regions to be etched to different depths, enabling precise thickness control for varying device requirements while simplifying the overall etching process through region-specific processing
Solution Approach 2:
The patent applies local quality by creating distinct thickness zones within the same FeRAM device structure. The recessed regions have reduced thickness compared to non-recessed regions, allowing each zone to be optimized for its specific function. This local differentiation enables precise manufacturing control without requiring complex global etching parameters
2Adaptability or versatility
If FeRAM devices are integrated on the same plane as logic interconnects, then system functionality is maintained, but height constraints and varying material thicknesses create fabrication challenges
Solution Approach 1:
The patent resolves the integration challenge by transitioning from a two-dimensional planar integration approach to a three-dimensional solution using recessed regions. By creating depth variations (first thickness vs. second thickness) within the same planar footprint, the patent enables FeRAM devices to coexist with logic interconnects on the same plane while accommodating different height requirements through vertical dimensionality
3Quantity of substance
If high-density FeRAM arrays are formed, then memory capacity increases, but the difficulty of etching and forming devices with precise thickness control increases
Solution Approach 1:
The patent applies preliminary action by pre-defining the recessed regions and their first thickness before final device formation. This preliminary structuring creates a template that guides subsequent etching and material deposition processes, enabling high-density array formation with precise thickness control. The recessed regions are prepared in advance to receive specific materials or structures, simplifying the overall fabrication sequence
Data Source
AI summary
A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.