Pocketed Copper Interconnect for Solder Ball Attachment Without Solder Resist

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Solution Overview

Problem

As semiconductor package sizes decrease, the absence of a solder resist layer complicates solder ball attachment, necessitating the development of alternative methods for ensuring reliable and efficient solder ball placement without the protective and structural benefits provided by the solder resist layer.

Innovation Solution

The introduction of pocketed regions within passivity layers, specifically using a silicon nitride (SiNx) film as a passivating layer to mimic the solder resist function, allowing for solder ball encapsulation and attachment within these regions, thereby eliminating the need for a solder resist layer and enabling thinner, more efficient substrate packages with smooth copper interfaces for high-speed input/output (HSIO) applications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a solder resist layer is used to protect copper surfaces and enable solder ball attachment, then reliability of solder ball attachment is improved, but device complexity and package thickness increase

Engineering Contradiction:
Improvesolder ball attachment reliabilityVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the essential function of the solder resist layer (enabling solder ball attachment) and relocates it to pocketed regions formed within the passivation layer itself. This eliminates the need for a separate solder resist layer, reducing package complexity while maintaining the solder ball attachment capability through localized copper pocket structures that expose copper surfaces for solder bonding.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a planar solder resist layer to three-dimensional pocketed regions within the passivation layer. By creating recessed copper pockets that extend vertically into the passivation layer, the solution enables solder ball attachment in a different spatial dimension, eliminating the need for a separate solder resist layer and reducing overall package thickness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If a solder resist layer is used to provide structural benefits for solder ball attachment, then solder ball attachment reliability is improved, but package thickness increases

Engineering Contradiction:
Improvesolder ball attachment reliabilityVSAvoidpackage thickness
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent nests the copper pocket structures within the passivation layer itself, creating recessed regions that contain the copper surfaces needed for solder ball attachment. This nesting approach integrates the solder ball attachment function within the existing passivation layer structure, eliminating the need for an additional solder resist layer and reducing overall package thickness.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Speed

If smooth copper is included on the metal layer for HSIO applications, then high-speed input/output performance is improved, but integration with first layer interconnect surface finish becomes complex

Engineering Contradiction:
Improvehigh-speed input/output performanceVSAvoidsurface finish integration complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent applies different surface qualities to different regions: smooth copper surfaces are maintained in the pocketed regions for HSIO signal routing to ensure high-speed performance, while the surrounding areas use standard surface finishes for interconnect integration. This localized approach allows simultaneous optimization for both high-speed signaling and robust interconnect attachment without requiring complex integration schemes.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240006291A1Pocketed copper in first layer interconnect and method
Publication Date: 2024.01.04 INTEL CORP
  • US20240006291A1 patent drawing
  • US20240006291A1 patent drawing
  • US20240006291A1 patent drawing

AI summary

A substrate package comprises a substrate comprised of buildup layers. The substrate package can further include a passivating layer connected to the substrate and including a pocketed region. The pocketed region can include a first portion thinner than a second portion extending from the first portion. The substrate package can further include a solder ball encapsulated within the pocketed region. Other systems, apparatuses and methods are described.