Programmable On-Chip Logic Analyzer for Selective Signal Capture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current automatic test equipment (ATE) logic analyzers face challenges in efficiently capturing and analyzing signals on digital signal lines or logic chip pins over time, particularly in mixed-signal environments, where limited on-die space and varying clock frequencies complicate data capture and analysis.
Innovation Solution
A programmable on-chip logic analyzer (POCLA) with an event-trigger state machine and programmable filter modules that selectively capture and store relevant signal states based on programmable conditions, allowing for efficient data analysis and storage of targeted data, even in high-speed environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If traditional logic analyzers capture all signal states on digital signal lines, then complete data coverage is achieved, but on-die space is excessively consumed
Solution Approach 1:
The patent extracts and stores only the relevant signal states that meet programmable capture conditions rather than capturing all signal states. The capture logic selectively extracts data based on user-defined criteria, storing only the necessary information in on-die memory, thereby reducing space consumption while maintaining data coverage for analysis.
Solution Approach 2:
The patent applies different capture qualities to different signal lines by allowing selective enabling of capture for specific signals based on their importance. Not all signals are captured with the same depth or frequency - only those meeting programmable conditions are stored, creating local quality differentiation in data capture.
2Measurement precision
If logic analyzers operate at high clock frequencies, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal capture logic unit that can operate across multiple clock domains and frequencies. The same hardware infrastructure handles both high-frequency and low-frequency signals, reducing overall device complexity while maintaining measurement precision through programmable triggering and capturing mechanisms.
Solution Approach 2:
The patent introduces programmable capture conditions and event-triggered capturing that dynamically adapt to different signal frequencies and patterns. The capture logic can adjust its behavior based on detected events, allowing precise capture at variable rates rather than requiring continuous high-speed capture of all signals.
3Loss of information
If programmable capture conditions are implemented, then data relevance is improved, but device complexity increases
Solution Approach 1:
The patent implements preliminary configuration of capture conditions through programmable setup before actual signal capture begins. Users pre-define capture triggers, patterns, and conditions that the logic analyzer then automatically executes, eliminating the need for complex real-time decision logic while improving data relevance through targeted capture.
Solution Approach 2:
The capture logic automatically evaluates programmable conditions and self-manages the capture process without external intervention. Once conditions are programmed, the system autonomously determines which signal states to capture and store, reducing operational complexity while maintaining high data relevance through condition-based filtering.
Data Source
AI summary
Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed.


