POD Termination with Adaptive Reference Voltage for I/O Channels

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current flash memory systems face challenges in achieving high performance and low power consumption due to improper impedance matching in I/O channels, particularly at microwave frequencies, leading to signal reflections and degraded transmission speed.

Innovation Solution

Implementing pseudo open-drain (POD) termination with adaptive reference voltage adjustments in receiver circuits to alleviate non-linear driver issues, reducing power consumption and improving signal integrity by renormalizing asymmetric signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional center-tapped termination is used in I/O channels, then impedance matching is achieved, but power consumption is high

Engineering Contradiction:
Improvesignal integrityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the termination configuration from conventional center-tapped to pseudo open-drain (POD) termination, modifying the electrical parameters of the I/O channel to reduce power consumption while maintaining signal integrity through adaptive reference voltage adjustment

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces adaptive reference voltage adjustment that dynamically compensates for signal asymmetry caused by POD termination and non-linear drivers, allowing the system to adapt to varying operating conditions and maintain optimal performance

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If POD termination is used to reduce power consumption, then power efficiency improves, but signal asymmetry and non-linear driver issues arise

Engineering Contradiction:
Improvepower consumptionVSAvoidsignal integrity
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent implements adaptive reference voltage adjustment that responds to signal conditions in the I/O channel, automatically compensating for asymmetry and non-linear effects to maintain signal integrity while using POD termination

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically adjusts the reference voltage parameter to compensate for the asymmetric signal levels caused by POD termination, transforming the signal characteristics to restore proper logic level differentiation

Inventive Principle:
Principle #35Parameter changes

3Productivity

If high speed data transmission is implemented in multi-die systems, then productivity increases, but signal reflections and transmission degradation occur

Engineering Contradiction:
Improvedata transmission speedVSAvoidsignal quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent employs adaptive reference voltage adjustment that dynamically compensates for signal degradation and reflections in high-speed multi-die I/O channels, maintaining signal quality despite increased transmission speeds

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent modifies the reference voltage parameter adaptively to counteract signal reflections and transmission losses, enabling high-speed data transmission while maintaining signal integrity across multiple dies

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8923065B2Nonvolatile memory and method with improved I/O interface
Publication Date: 2014.12.30 SANDISK TECHNOLOGIES LLC
  • US8923065B2 patent drawing
  • US8923065B2 patent drawing
  • US8923065B2 patent drawing

AI summary

Each I/O channel between a controller and one or more memory dice of a memory device has a driver on one end and a receiver at the other end. The receiver is optionally terminated with a pseudo open-drain (“POD”) termination instead of the conventional center-tapped (“CTT”) termination to save energy. During a read operation, data is driven from the memory die to a POD terminated receiver circuit in the controller. With POD termination, the degradation in performance due to the more non-linear driver in the memory die, fabricated for example in the NAND technology processing, is alleviated by an adaptive reference voltage level adjustment in the receiver circuit of the controller. Optionally, the receiver circuit of a memory die is also provided with an adaptive reference level adjustment.