Center-Tapped PoDL Transformer Biasing for Balanced AC-Coupling
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Solution Overview
Problem
In Power over Data Lines (PoDL) systems, AC-coupling capacitors experience unequal effective values due to different DC bias voltages, leading to unbalanced data paths and potential conversion of common mode noise into differential signals, affecting data accuracy and efficiency.
Innovation Solution
The use of a resistor divider to generate a voltage of VPSE/2, which is applied across both AC-coupling capacitors, ensuring they have equal effective values and maintaining balance in data paths, while a center-tapped transformer and common mode choke further attenuate noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If AC-coupling capacitors are used in PoDL systems, then DC voltage blocking is achieved, but unequal effective capacitance values occur due to different DC bias voltages
Solution Approach 1:
A center-tapped transformer is introduced as an intermediary component between the PSE power supply and the AC-coupling capacitors. The transformer's center tap provides a midpoint reference that divides the DC voltage equally across both capacitors, ensuring equal effective capacitance values while maintaining DC blocking functionality.
Solution Approach 2:
The center-tapped transformer creates equipotential points at its terminals, establishing equal voltage potentials across both AC-coupling capacitors. This ensures that both capacitors experience identical DC bias conditions, resulting in equal effective capacitance values and balanced data paths.
2Volume of moving object
If ceramic capacitors are used for AC-coupling, then small size is achieved, but effective capacitance reduces significantly under DC bias voltage
Solution Approach 1:
The center-tapped transformer creates equipotential conditions that equalize the DC bias voltage across both ceramic capacitors. By ensuring both capacitors experience identical voltage stress, the solution maintains predictable and equal effective capacitance values despite the inherent voltage coefficient effects of ceramic materials.
3Object-affected harmful factors
If unequal capacitor values are present, then data path balance is affected, but common mode noise conversion into differential signals occurs
Solution Approach 1:
The center-tapped transformer establishes equipotential reference points that ensure symmetric voltage distribution across both AC-coupling capacitors. This symmetry maintains balanced data paths and prevents the conversion of common mode noise into differential signals by eliminating capacitance value disparities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in balanced data paths, preventing common mode noise conversion into differential signals, enhancing data accuracy and efficiency by maintaining equal effective capacitances across capacitors.
Implementation Method 1
the other ends of both capacitors are coupled to a voltage of approximately VPSE/2, generated by a resistor divider
Implementation Method 2
The capacitors C1 and C1 prevent DC voltage being coupled to the PHY 10 inputs
Implementation Method 3
a center-tapped transformer 26 is used to galvanically isolate the PHY 10 from the wires 14 and 16. The PHY signals are magnetically coupled to the wire pair.
Implementation Method 4
DC-coupling inductors L1 and L2 provide a high impedance to the data signals and a low impedance to the DC voltage
Implementation Method 5
common mode choke further attenuate noise
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A PoDL system that uses a center-tapped transformer, for galvanic isolation of the PHY, has AC-coupling capacitors in series between the transmission wires and the transformer's secondary windings for blocking DC voltages generated by a PSE power supply. The center tap is conventionally connected to ground. As a result, one capacitor sees the full VPSE voltage across it, and the other capacitor sees approximately 0V across it. Since the effective value of a ceramic capacitor significantly reduces with increasing DC bias voltages across it, the effective values of the capacitors will be very different, resulting in unbalanced data paths. This can lead to conversion of common mode noise and corrupt the data. To avoid this, a resistor divider is used to generate VPSE/2, and this voltage is applied to the center tap of the transformer. Therefore, the DC voltage across each capacitor is approximately VPSE/2, so their values remain equal.