POE Module Packet Scheduling for Multi-Core Efficiency

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Solution Overview

Problem

Multi-Core Processors face challenges in maintaining packet order due to varying processing delays across cores, leading to inefficiencies in communication networks, particularly in pipeline processing modes where cores wait for previous operations to complete, affecting overall processing efficiency.

Innovation Solution

A data processing method and system that employs a POE module to store and manage packets in FIFO order, using Get_packet and tag switching commands to ensure packets are processed and switched between cores according to a preset scheduling rule, allowing cores to continue other tasks without waiting for previous cores to finish, thus reducing waiting time and improving efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cores wait for previous cores to finish writing operation before proceeding, then packet order is maintained, but core processing efficiency deteriorates

Engineering Contradiction:
Improvepacket orderVSAvoidcore processing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the packet processing workflow into distinct phases: reading operation, processing operation, and writing operation. Each core can independently execute these phases without blocking other cores, as the POE module manages the sequencing and coordination of these segmented operations across multiple cores.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The POE module acts as an intermediary between multiple cores and the packet buffer. It receives commands from cores, manages packet distribution, and coordinates the reading, processing, and writing operations. This intermediary abstracts the complexity of inter-core synchronization, allowing cores to operate independently while maintaining packet order through centralized management.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple cores process packets in parallel, then processing speed increases, but packet order may be disordered due to varying processing delays

Engineering Contradiction:
Improveprocessing speedVSAvoidpacket order
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where cores report their processing status to the POE module through commands. The POE module receives completion notifications and uses this feedback information to dynamically adjust packet distribution, ensuring that packets are transferred to subsequent cores in the correct FIFO order based on actual processing completion status.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The POE module performs preliminary actions by pre-managing the packet buffer and preparing packets for distribution. It anticipates processing completion by monitoring core status and proactively manages the timing of packet transfers to subsequent cores, ensuring order is maintained before actual processing delays can cause disorganization.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8848532B2Method and system for processing data
Publication Date: 2014.09.30 HUAWEI TECH CO LTD
  • US8848532B2 patent drawing
  • US8848532B2 patent drawing
  • US8848532B2 patent drawing

AI summary

A data processing method and system and relevant devices are provided to improve the processing efficiency of cores. The method includes: storing received packets in a same stream sequentially; receiving a Get_packet command sent by each core; selecting, according to a preset scheduling rule, packets for being processed by each core among the stored packets; receiving a tag switching command sent by each core, where the tag switching command indicates that the core has finished a current processing stage; and performing tag switching for the packets in First In First Out (FIFO) order, and allocating the packets to a subsequent core according to the Get_packet command sent by the subsequent core after completion of the tag switching, so that the packet processing continues until all processing stages are finished. A data processing system and relevant devices are provided. With the present invention, the processing efficiency of cores may be improved.