Point Processor Array Layout for Faster PDE Solving

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Solution Overview

Problem

Current computer systems face inefficiencies in solving partial differential equations, particularly for large domain sizes and complex boundary conditions, leading to prolonged simulation times and limited speedup with parallel computing due to data transfer bottlenecks and Amdahl's law limitations.

Innovation Solution

A specialized computer architecture with an array of point processors, each comprising tiles with computational elements and routers, configured to solve partial differential equations efficiently by pre-scheduling data and computational requirements at compile time, minimizing dynamic scheduling and optimizing on-chip computation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If general-purpose computer systems are used to solve partial differential equations, then versatility in solving different types of equations is maintained, but computational efficiency and simulation time are significantly reduced

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidarchitecture specialization
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system segments the computational domain into discrete grid points and organizes point processors in an array where each processor handles specific spatial locations. This segmentation allows parallel processing of different domain regions while maintaining overall system coherence through the router network.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The router acts as an intermediary component that mediates data flow between point processors and memory systems. It manages data routing, buffering, and synchronization, enabling efficient communication without bottlenecks while preserving architectural modularity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If parallel computing is used to speed up simulations, then processing capacity increases, but data transfer bottlenecks and Amdahl's law limitations reduce the actual speedup achieved

Engineering Contradiction:
Improvesimulation speedupVSAvoiddata transfer time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The architecture merges computation and data storage functions into an integrated array structure where point processors are closely coupled with local data buffers. This merging reduces data transfer distances and enables compute-bound rather than memory-bound operations, overcoming traditional data transfer bottlenecks.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system introduces a spatial dimension to data organization by arranging point processors and data in a geometric array that mirrors the physical domain being simulated. This spatial mapping optimizes data access patterns and enables efficient neighbor-to-neighbor communication without centralized bottlenecks.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If dynamic scheduling is used during runtime to manage computations, then adaptability to different problem types is improved, but computational overhead and simulation time increase

Engineering Contradiction:
Improveproblem type flexibilityVSAvoidscheduling overhead
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system performs preliminary configuration of the point processor array at compile time based on the specific partial differential equation and domain characteristics. This pre-scheduling determines the optimal mapping of computational tasks to processors before runtime, eliminating the need for dynamic scheduling overhead during simulation execution.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The architecture allows runtime adaptation through parameter changes in the configuration rather than structural reconfiguration. Problem-specific parameters such as boundary conditions, domain size, and equation coefficients can be adjusted without requiring dynamic scheduling, maintaining both adaptability and efficiency.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12572618B2Point processor array for solving partial differential equations
Publication Date: 2026.03.10 VORTICITY INC
  • US12572618B2 patent drawing
  • US12572618B2 patent drawing
  • US12572618B2 patent drawing

AI summary

Embodiments relate to a system for solving partial differential equations. The system receives problem packages corresponding to problems to be solved, each comprising at least a partial differential equation and a domain. A solver stores a plurality of nodes of the domain corresponding to a first time-step, and processes the nodes over a plurality of time-steps using an array of point processors. Each point processor comprises a series of tiles, each having a computational element and a router, and are configured and connected based on a discretized form of the partial differential equation, to allow each point processor to receive a node of the domain and generate a value for the node for a next time step. Because all the data and computational requirements of the point processors are determined at compile time, no dynamic scheduling needs to be performed, allowing for more efficient usage of computational resources.