Point-to-Point Interconnects Reduce Data Transfer Latency
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Solution Overview
Problem
Server computers using ring topologies for interconnects between integrated circuits (ICs) face inefficiencies in data transfer, leading to higher latency and lower throughput due to the number of hops data needs to take across the ring, especially as the number of ICs increases to support higher processing power or memory capacity.
Innovation Solution
Implementing a point-to-point interconnect architecture where each IC is connected to all other ICs via dedicated links, allowing data to be split into multiple cells and transmitted through intermediate ICs, utilizing a credit-based flow control protocol to manage bandwidth and ensure efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If ring topology interconnects are used between ICs, then the system can support multiple ICs with relatively simple wiring, but data transfer latency increases and throughput decreases as the number of hops between source and destination ICs increases
Solution Approach 1:
The patent segments the data transfer path by introducing intermediate ICs that act as independent relay nodes. Each IC is divided into separate transmit and receive channels, allowing data to be segmented across multiple parallel paths rather than following a single sequential ring path, thereby reducing latency while maintaining wiring simplicity.
Solution Approach 2:
The patent introduces intermediate ICs as mediators in the data transfer path. These intermediate ICs receive data from source ICs and forward it to destination ICs, enabling direct two-way communication without requiring data to traverse the entire ring. This intermediary approach reduces the number of hops and latency while preserving the simple ring wiring topology.
2Ease of manufacture
If ring topology interconnects are used between ICs, then the system can be easily manufactured with standardized connections, but data transfer throughput is limited by the sequential nature of ring-based data flow
Solution Approach 1:
The patent segments data into multiple cells that can be transmitted simultaneously through different IC paths. Each IC processes and forwards data cells independently, enabling parallel data flow that increases throughput while maintaining the standardized ring connection structure that ensures ease of manufacture.
Solution Approach 2:
The patent implements dynamic data cell transmission where intermediate ICs can adaptively forward data cells based on available bandwidth and destination requirements. This dynamic approach allows the system to maximize throughput by utilizing all available IC paths simultaneously, while the underlying ring topology remains static and easy to manufacture.
3Quantity of substance
If the number of ICs is increased to support higher processing power and memory capacity, then the system can handle more workloads, but data transfer latency increases due to the greater number of hops required in ring topology
Solution Approach 1:
The patent uses intermediate ICs as mediators that enable direct data transfer between any pair of ICs regardless of their position in the ring. When ICs are increased in number, these intermediaries ensure that data does not need to traverse the entire expanded ring, thereby preventing latency from increasing proportionally with the number of ICs.
Solution Approach 2:
The patent segments the data transfer task across multiple intermediate ICs, allowing data to be forwarded through the most efficient path rather than following the sequential ring order. This segmentation approach ensures that adding more ICs increases capacity without necessarily increasing the hop count for any given data transfer.
4Productivity
If dedicated point-to-point interconnects are implemented between all ICs, then data transfer bandwidth can be maximized, but the complexity of the interconnect system increases significantly
Solution Approach 1:
The patent makes each IC universally capable of both receiving and transmitting data cells to any other IC in the system. This multi-functionality allows any IC to act as an intermediate node, eliminating the need for dedicated point-to-point interconnects between all pairs of ICs while still achieving maximum bandwidth utilization through the existing ring structure.
Solution Approach 2:
The patent merges the functions of multiple potential interconnect paths into the existing ring topology by enabling bidirectional data flow through intermediate ICs. Instead of implementing separate dedicated interconnects for each IC pair, the system merges all communication needs into the shared ring infrastructure, reducing overall complexity while maintaining high bandwidth capability.
Data Source
AI summary
In a computer comprising a plurality of integrated circuits (ICs), each IC may be connected to all other ICs via a respective point-to-point interconnect. A source IC divides the data to be transmitted to a destination IC for a transaction to generate multiple data cells so that each data cell includes a different portion of the data. The source IC transmits one of the data cells to the destination IC and remaining data cells to intermediate ICs, wherein an intermediate IC is an IC other than the source IC or the destination IC. The intermediate ICs forward the remaining data cells to the destination IC.