Point-to-Point Memory Architecture Reducing Latency and Pin Count
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Solution Overview
Problem
Existing memory architectures face limitations in throughput due to signal reflections from multi-drop connections, capacity constraints due to word width, and increased complexity and cost from Fully Buffered Dual In-Line Memory Modules (FB-DIMMs), which also introduce latency and require matched data widths between memory controllers and components.
Innovation Solution
A point-to-point memory architecture with direct connections between memory components and a memory controller, utilizing a daisy-chained address bus and serial data buses, allowing for flexible configuration and reduced pin count, enabling different memory widths and depths without the need for buffering or queuing, thus minimizing latency and enhancing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multi-drop connections are used from memory controller to memory components, then pin count is reduced and routing is simplified, but signal reflections occur that limit throughput and high frequency operation
Solution Approach 1:
The patent segments the memory system into multiple independent point-to-point connections between the memory controller and memory components. Instead of a shared multi-drop bus, each memory component receives dedicated connections for address/command and data transfers. This segmentation eliminates signal reflections while maintaining routing simplicity, as each connection is isolated and does not interfere with others.
2Quantity of substance
If word width is increased to expand memory capacity, then storage capacity increases, but data bus routing becomes increasingly difficult and complex
Solution Approach 1:
The patent transitions from a single wide data bus to multiple narrower point-to-point data connections. Instead of routing one complex wide bus across the board, the system uses multiple independent connections that can be routed more easily. Each connection carries a portion of the data, and the memory controller manages these multiple connections to achieve the required total bandwidth and capacity.
3Quantity of substance
If word width is increased to expand memory capacity, then storage capacity increases, but pin count increases which greatly adds to manufacturing cost
Solution Approach 1:
The patent segments the data path into multiple point-to-point connections, each with their own dedicated data bus. This allows the system to achieve high capacity through parallel connections rather than a single wide bus. The segmentation enables better pin utilization and reduces the need for excessive pins on individual components, as the memory controller manages multiple narrower connections efficiently.
4Device complexity
If Fully Buffered Dual In-Line Memory Modules (FB-DIMMs) are used to address limitations, then pin count on memory controller is reduced and bus routing is simplified, but latency increases due to buffering and queuing processes
Solution Approach 1:
The patent extracts the buffering function from the memory module (as in FB-DIMMs) and eliminates the intermediate buffer entirely. Instead of controller → buffer → memory component, the system implements direct point-to-point connections from the memory controller to each memory component. This extraction of the buffering intermediate element eliminates the associated latency while maintaining simplified routing through dedicated connections.
5Adaptability or versatility
If memory controller data width is matched to memory component data width, then compatibility is achieved, but pin count on both memory controller and memory components increases
Solution Approach 1:
The patent implements dynamic data width configuration through point-to-point connections. The memory controller can dynamically allocate and configure data connections based on the specific memory components installed. Each memory component connects with its own dedicated data bus width, allowing the system to achieve compatibility across different component types without requiring all components to have matching high pin counts. The controller manages these variable-width connections efficiently.
Data Source
AI summary
In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.