Pointer Counter Memory Allocation for Concurrent Data Access

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Distributed storage systems face bottlenecks and data inconsistencies due to atomic operations that prevent concurrent access for writers and readers, leading to incomplete or frozen data states during write and read transactions.

Innovation Solution

A computing device manages pointer counters for memory locations, allowing concurrent atomic access by blocking access when necessary, incrementing counters for read transactions, and deallocating memory when counters reach zero, ensuring data integrity and availability during write and read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If atomic operations are used to update data in the non-transitory data store, then data consistency is ensured, but concurrent access between writers and readers is blocked

Engineering Contradiction:
Improvedata consistencyVSAvoidconcurrent access efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the data storage into multiple memory locations (first memory location, second memory location, etc.) and uses pointer counters to manage access to each segment. This allows different memory locations to be accessed concurrently by different transactions, resolving the contradiction between data consistency and concurrent access efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces pointer counters as intermediary mechanisms that mediate between writers and readers. The pointer counters track the state of each memory location and coordinate access without requiring blocking atomic operations, enabling concurrent access while maintaining data consistency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If writers freeze access to memory locations during write transactions, then data integrity is maintained, but read transactions are blocked and system efficiency decreases

Engineering Contradiction:
Improvedata integrityVSAvoidtransaction waiting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements dynamic access control where the state of memory locations changes based on transaction progress. Memory locations transition between locked and unlocked states dynamically, allowing readers to access completed writes while writers continue their operations, reducing waiting time without compromising data integrity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent performs preliminary actions by allocating multiple memory locations in advance and initializing pointer counters before write transactions begin. This preparation enables seamless switching between memory locations during writes, preventing blocking of read transactions and reducing overall transaction waiting time.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If readers retrieve data during ongoing write transactions, then read efficiency is improved, but data completeness and consistency are compromised

Engineering Contradiction:
Improveread efficiencyVSAvoiddata completeness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent uses pointer counters as feedback mechanisms that provide real-time information about the state of memory locations. Readers query the pointer counter status before accessing data, ensuring they only retrieve complete and consistent data, while maintaining high read efficiency through non-blocking access to available data.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9477516B1Concurrent in-memory data publication and storage system
Publication Date: 2016.10.25 GOOGLE LLC
  • US9477516B1 patent drawing
  • US9477516B1 patent drawing
  • US9477516B1 patent drawing

AI summary

A method includes allocating a first memory location in a non-transitory data store in communication with a computing device and writing data to the first memory location when a first write transaction executes on the non-transitory data store. The method further includes executing one or more read transactions on the first memory location after completion of the first write transaction and incrementing a first pointer counter upon completion of the first write transaction and for each read transaction executing on the first memory location. The method allocates a second memory location in the non-transitory data store and writes updated data to the second memory location when a second write transaction executes on the non-transitory data store to update the data. The first pointer counter decrements and the second pointer counter increments upon completion of the second write transaction. The first memory location de-allocates when the first pointer counter is zero.