Pointer Fetch Address Translation Caching for NVMe Page Miss Handling
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Solution Overview
Problem
The continual need for address translations in memory systems, particularly in systems with multiple non-volatile memory express (NVMe) devices, leads to performance bottlenecks in terms of speed, latency, and quality-of-service due to increased I/O traffic and the need to move data across PCIe buses, which affects the efficiency of memory command handling.
Innovation Solution
Implementing an address translation cache (ATC) within the host interface circuitry to store address translations for future access, and incorporating a page request interface (PRI) handler to automate page miss requests, reducing the need for pinning large amounts of host memory and minimizing cache misses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If address translations are performed continually in memory systems with multiple NVMe devices, then data can be accessed across different memory devices, but I/O traffic increases and performance bottlenecks occur due to repeated PCIe bus transactions
Solution Approach 1:
The system performs address translations in advance and stores them in a translation cache before they are needed for actual data access. When a memory command arrives, the translation is already available, eliminating the need for real-time PCIe bus transactions and reducing I/O latency.
Solution Approach 2:
A translation cache is introduced as an intermediary component between the host interface and the memory devices. This cache stores pre-fetched address translations and provides them locally, reducing the need for repeated PCIe bus transactions and improving overall system throughput.
2Speed
If address translation requests are processed in real-time, then data access can proceed without delay, but the system requires pinning large amounts of host memory to handle translation requests
Solution Approach 1:
The system extracts the address translation data from host memory and stores it in a dedicated translation cache within the memory sub-system. This separation allows the system to maintain fast data access while reducing the amount of host memory that needs to be pinned for translation operations.
Solution Approach 2:
The memory sub-system performs address translations using its own local cache resources rather than relying on host memory. The translation cache serves itself by storing and providing translations locally, eliminating the need to pin large amounts of host memory while maintaining fast access speeds.
3Productivity
If the address translation cache is implemented, then cache hits reduce I/O traffic, but cache misses require additional page request handling
Solution Approach 1:
The translation cache is designed to autonomously handle miss events by automatically generating page requests and updating itself with new translations. This self-service mechanism reduces the burden on the host system and simplifies cache management while maintaining high throughput through efficient cache hits.
Data Source
AI summary
A method, performed by pointer fetch circuitry, includes buffering, in a pointer buffer of host interface circuitry, pointers associated with chop commands of a logical block address read command residing in a submission queue of a host system. The method includes sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit includes a subset of the pointers. The method includes detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command. The method includes sending a translation miss message to a page request interface (PRI) handler. The translation miss message contains a virtual address of the translation unit and a restart point for the chop command, the translation miss message to trigger the PRI handler to send a page miss request to a translation agent of the host system.