Pointer Matching Across Memory Hierarchy Levels
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Solution Overview
Problem
Capability-based systems face challenges in providing fine-grained memory protection, especially in rack-scale systems with large non-volatile memories, due to the assumption that virtual addresses always point to the same physical memory, which is compromised by the need for memory sharing and the persistence of byte addressable data beyond process lifetimes, leading to security vulnerabilities and unauthorized access.
Innovation Solution
The system extends traditional capabilities by including additional physical address spaces and implements a pointer matching mechanism across levels of a memory hierarchy, using a memory accessor, pointer loader, pointer handler, location matcher, and exception handler to ensure that physical addresses match the mapped ones, raising exceptions for mismatches and allowing for dynamic re-mapping or adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional capability-based systems assume virtual addresses always point to the same physical memory, then memory access is simple and fast, but security protection is compromised when memory sharing and persistence are needed
Solution Approach 1:
The patent segments the memory hierarchy into multiple levels (first level with first virtual-to-physical address mapping, second level with second virtual-to-physical address mapping). By dividing the address translation into separate segments at different levels, the system can independently manage and validate mappings at each level, enabling fine-grained security control without requiring a complete redesign of the memory architecture.
Solution Approach 2:
The patent introduces an intermediary validation mechanism that checks whether the first physical address (from first-level mapping) matches the second physical address (from second-level mapping) before allowing memory access. This intermediary check acts as a mediator between the two address mapping levels, ensuring consistency and security without requiring direct manipulation of either mapping level alone.
2Reliability
If page-level hardware protection is used, then implementation is simple, but fine-grained memory protection is insufficient to prevent unauthorized access within a page
Solution Approach 1:
The patent applies segmentation by introducing capability-based protection at the byte level within pages. Instead of treating entire pages as a single protection unit, the system divides protection into finer granules by associating capabilities with specific byte ranges, allowing independent access control for each capability while maintaining the simplicity of page-level hardware protection as a foundation.
Solution Approach 2:
The patent implements nested protection by placing capability-based fine-grained protection inside the page-level hardware protection framework. Capabilities are nested within pages, and the validation mechanism is nested within the address translation process. This nested structure enables multiple levels of protection to coexist without requiring complete replacement of existing hardware mechanisms.
3Reliability
If capabilities are used for fine-grained memory protection, then unauthorized access is prevented, but the assumption that virtual addresses always point to the same physical memory is compromised by memory sharing and persistence
Solution Approach 1:
The patent applies dynamics by making the address mapping relationships changeable rather than fixed. The validation mechanism dynamically checks whether the first physical address matches the second physical address at runtime, allowing the system to adapt to memory sharing scenarios where mappings may differ. This dynamic validation enables capabilities to maintain their access control function while accommodating flexible memory sharing and persistence requirements.
Solution Approach 2:
The patent introduces feedback by implementing a validation mechanism that provides feedback about address mapping consistency. When a memory access occurs, the system feedbacks whether the first and second physical addresses match, and based on this feedback, either allows or blocks the access. This feedback loop enables the system to adapt to changing memory configurations while maintaining secure access control.
Data Source
AI summary
In one example in accordance with the present disclosure, a system may comprise a memory accessor to access a memory and a pointer loader to load a virtual address (VA) pointer corresponding to a first location in the memory and a physical address (PA) pointer corresponding to the VA pointer. The system may comprise a pointer handler to determine a first physical address in the memory mapped to the first location in the memory and a location matcher to determine whether the second physical address mapped to the PA pointer matches the first physical address. The system may also comprise an exception handler to raise an exception when the second physical address does not match the first physical address.