Combined Polar-BCH ECC Decoding for NAND Read Throughput
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Solution Overview
Problem
NAND memory devices face challenges in achieving high read throughput and low latency with low power consumption and complexity, necessitating effective error correction codes (ECCs) that balance complexity and performance across hard decision (HD) and soft decision (SD) channels.
Innovation Solution
A combined ECC scheme integrating BCH-GCC and Polar-GCC codes, leveraging their mutual optimization and decoding algorithms, is employed to decode ECC noisy codewords using a first or second decoder based on channel conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single bit from the NAND channel is measured per bit that is written (hard decision binary channel), then read throughput is improved and latency is reduced, but error correction capability deteriorates
Solution Approach 1:
The patent combines BCH-GCC and Polar-GCC decoding approaches into a unified decoding system. The processing circuitry integrates both decoders and selectively applies them based on error patterns, merging the strengths of algebraic codes (good for HD channels) and polar codes (good for SD channels) to maintain error correction capability while using hard decision channels for high throughput.
Solution Approach 2:
The patent implements dynamic decoder selection where the processing circuitry determines which decoder (BCH-GCC or Polar-GCC) to use based on the specific error patterns detected in the read data. This dynamic adaptation allows the system to optimize between speed and error correction capability for each decoding operation.
2Reliability
If effective error correcting codes (ECCs) are implemented for hard decision channels, then error correction performance is improved, but decoding complexity increases
Solution Approach 1:
The patent segments the error correction task into two distinct decoding paths: BCH-GCC decoding for hard decision channels and Polar-GCC decoding for soft decision channels. This segmentation allows each decoder to be optimized for its specific channel type, reducing the complexity burden on any single decoder while maintaining overall error correction performance.
Solution Approach 2:
The patent introduces an intermediary selection mechanism that determines which decoder to use based on the characteristics of the received data. This intermediary layer manages the complexity by routing appropriate data to the appropriate decoder, preventing the system from needing to implement both full decoding capabilities simultaneously for all data types.
3Productivity
If multiple read operations are performed to achieve high read throughput, then read throughput is improved, but latency and power consumption increase
Solution Approach 1:
The patent enables the decoding system to self-determine the appropriate decoding approach based on the error patterns in the received data. By using the inherent characteristics of the data itself to guide the decoding process, the system avoids unnecessary additional read operations while maintaining high throughput and low latency.
Data Source
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AI summary
A nonvolatile memory device includes a memory and processing circuitry configured to receive a read request from a host, read an ECC noisy codeword from the memory based on the read request, determine to decode the ECC noisy codeword using a first decoder or a second decoder, and decode the ECC noisy codeword using the determined decoder.