Polar Coding Bit Pattern Generation for Flexible Block Conditioning
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Solution Overview
Problem
Existing polar coding implementations face challenges in achieving flexibility to insert or remove bits or soft bits from arbitrary positions, particularly in flexible polar encoders and decoders where K, N, and M vary, leading to high hardware usage and long clock cycles.
Innovation Solution
An electronic device with a bit pattern generator that performs bit pattern generation over multiple clock cycles, using a counter and bank of comparators to process w bits in each cycle, and a bit pattern ROM to store pre-computed bit patterns, allowing parallel processing and reducing clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flexible polar coding operations are implemented to support varying K, N, and M values, then adaptability is improved, but device complexity increases due to high hardware usage
Solution Approach 1:
The patent divides the bit pattern generation into segments processed in parallel. The block conditioning circuit is divided into multiple parallel units, each handling a specific segment of the bit pattern generation. This segmentation allows the system to support flexible K, N, and M values without proportionally increasing overall hardware complexity, as each segment can be independently optimized and processed concurrently.
Solution Approach 2:
The patent introduces a time dimension by processing bit patterns in multiple clock cycles. Instead of generating the entire bit pattern in a single complex operation, the system generates bits sequentially over t = ⌈n/w⌉ clock cycles, where w bits are processed in parallel each cycle. This dimensional transformation from spatial to temporal processing reduces the peak hardware requirements while maintaining flexibility.
2Adaptability or versatility
If flexible polar coding operations are implemented to support varying K, N, and M values, then adaptability is improved, but processing time increases due to long clock cycles
Solution Approach 1:
The patent employs periodic action by organizing bit pattern generation into regular clock cycle intervals. The block conditioning circuit operates in a systematic periodic manner, processing w bits in each clock cycle according to a predetermined pattern. This periodic structure enables predictable timing and allows the system to efficiently handle varying K, N, and M values without excessive clock cycle extensions, as the processing rhythm is optimized for parallel bit generation.
3Productivity
If parallel processing is used to process w bits in each clock cycle, then productivity is improved, but device complexity increases due to additional hardware components
Solution Approach 1:
The patent designs the block conditioning circuit with universal components that can perform multiple functions. The same parallel processing units that generate bit patterns are also used for block conditioning operations. This multi-functionality allows the system to achieve high productivity in bit processing without proportionally increasing hardware complexity, as each component serves multiple purposes within the polar coding framework.
Data Source
AI summary
An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=┌n/w┐) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=┌n/w┐) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=┌n/w┐ clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value.