Polar Code Bit-Reversal Layout for Low-Latency Parallel Decoding

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Solution Overview

Problem

Polar encoding and decoding techniques suffer from high latency due to the inherent data dependencies in serial cancellation algorithms, limiting the exploitation of parallelization and resulting in low coding/decoding throughput in wireless communication systems.

Innovation Solution

Implementing a semi-parallel bit-reversal technique at the polar encoder and decoder, which involves determining indices for consecutive elements, bit-reversing binary sequences, and writing elements to memory banks in parallel based on the bit-reversed order, to reduce latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If serial cancellation decoding algorithm is used for polar decoding, then decoding accuracy is maintained, but latency is high and throughput is low

Engineering Contradiction:
Improvedecoding throughputVSAvoiddecoding latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The decoding process is segmented into multiple independent parallel paths by dividing the input bits into groups that can be processed simultaneously. Each parallel decoder processes a subset of bits independently, eliminating the sequential dependency that causes high latency in traditional serial cancellation decoding algorithms.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transforms the one-dimensional sequential processing into a multi-dimensional parallel processing structure. By organizing decoders in parallel stages and using bit-reversal permutation to redistribute data flow, the system achieves throughput improvement while maintaining decoding accuracy through the parallel architecture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If parallelization is attempted in serial cancellation decoding algorithm, then throughput may improve, but the inherent data dependencies prevent effective parallelization

Engineering Contradiction:
Improvecoding/decoding throughputVSAvoidparallelization complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Bit-reversal permutation is performed as a preliminary action before the parallel decoding process. This pre-processing step reorders the input bits according to bit-reversed indices, which enables the subsequent parallel decoders to process independent subsets of data without conflicting dependencies, thus facilitating effective parallelization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The bit-reversal permutation acts as an intermediary that transforms the input data into a format suitable for parallel processing. This intermediate transformation step decouples the data dependencies, allowing multiple parallel decoders to operate independently while still producing correct results when combined.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10476525B2Low latency bit-reversed polar codes
Publication Date: 2019.11.12 QUALCOMM INC
  • US10476525B2 patent drawing
  • US10476525B2 patent drawing
  • US10476525B2 patent drawing

AI summary

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In addition, the apparatus may bit reverse a binary sequence associated with each of the m consecutive elements. In an aspect, each of the m consecutive elements may include a different binary sequence. Further, the apparatus may determine a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m elements. In addition, the apparatus may write each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices.