Polar Transmitter Clock Interpolation for Phase Error Compensation
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Solution Overview
Problem
Digital polar transmitters face challenges in compensating for frequency deviation effects caused by variable-rate clocks, which can affect the accuracy of operations and are typically addressed by running a clock divider at a high clock rate, consuming power and area, making it unsuitable for resource-limited applications.
Innovation Solution
A polar transmitter design with a frequency modulating path that includes a direct feed input for modulating the oscillator frequency and a compensating feed input that uses resampling and interpolation to adjust for frequency modulation effects on phase errors, employing a resampling circuit, accumulator, and sampler to generate a reference phase output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high clock rate is used in the clock divider to compensate for frequency deviation effects, then the frequency deviation compensation effectiveness is improved, but the power consumption and area increase
Solution Approach 1:
The patent changes the clock rate parameter dynamically based on the operating mode. In normal mode, a lower clock rate is used to save power. When frequency deviation compensation is needed, the system switches to a higher clock rate temporarily. This dynamic parameter adjustment resolves the contradiction by having high reliability only when necessary while maintaining low power consumption during normal operation.
Solution Approach 2:
The system transitions from a static high clock rate approach to a dynamic clock rate approach. The clock divider adapts its operating frequency based on real-time requirements, switching between low and high clock rates. This dynamic behavior allows the system to achieve frequency deviation compensation effectiveness only when needed, thereby reducing overall power consumption and area requirements.
2Reliability
If a high clock rate is used in the clock divider to compensate for frequency deviation effects, then the frequency deviation compensation effectiveness is improved, but the area increases
Solution Approach 1:
The patent changes the clock rate parameter dynamically based on the operating mode. In normal mode, a lower clock rate is used to save power. When frequency deviation compensation is needed, the system switches to a higher clock rate temporarily. This dynamic parameter adjustment resolves the contradiction by having high reliability only when necessary while maintaining low power consumption during normal operation.
Solution Approach 2:
The system transitions from a static high clock rate approach to a dynamic clock rate approach. The clock divider adapts its operating frequency based on real-time requirements, switching between low and high clock rates. This dynamic behavior allows the system to achieve frequency deviation compensation effectiveness only when needed, thereby reducing overall power consumption and area requirements.
3Area of stationary object
If integer edge division is used to generate clocks from the frequency modulated clock, then the area and power are reduced, but the clock frequency becomes time-variant affecting transmitter circuit operations
Solution Approach 1:
The patent segments the clock generation process into two independent paths: a direct feed input path that maintains the original frequency modulated clock for area-efficient operation, and a compensating feed input path that processes the clock through integer edge division to generate a stable reference clock. This segmentation allows each path to serve its specific function, resolving the contradiction between area efficiency and frequency stability.
Solution Approach 2:
The patent introduces a compensating feed input as an intermediary mechanism. This intermediary takes the time-variant clock from integer edge division and uses it to compensate for frequency deviation effects in the direct feed path. By introducing this mediating element, the system achieves both area efficiency (through integer edge division) and frequency stability (through compensation).
Data Source
AI summary
A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result.