Polar Code Interleaving Matrix for Burst Error Randomization

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Solution Overview

Problem

Polar codes used in channel coding for higher order modulation suffer from poor error correction performance due to burst errors, and existing interleaving methods like row-column interleaving are ineffective in randomizing burst errors, while random interleaving requires excessive storage resources.

Innovation Solution

An interleaving method that writes bits into an interleaving matrix using quasi periodicity, ensuring bits are discontinuous across rows and columns, and employs specific read and write rules to improve error correction performance, including column transformation and varying bit allocations across columns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If random interleaving is used, then error correction performance is improved, but storage resources required are very large

Engineering Contradiction:
Improveerror correction performanceVSAvoidstorage resources
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the bit sequence into multiple groups and processes each group through different interleaving patterns. Instead of storing a complete permutation sequence for the entire long code, the system divides the interleaving task into smaller segments that can be handled with minimal storage, thereby resolving the contradiction between error correction performance and storage resource consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs periodic interleaving patterns where bits are written to and read from the interleaver in regular cycles. This periodic action creates effective randomization for error correction without requiring storage of large permutation sequences, as the same limited set of patterns is reused systematically throughout the coding process.

Inventive Principle:
Principle #19Periodic action

2Quantity of substance

If row-column interleaving is used, then storage resources are reduced, but error correction performance deteriorates in higher order modulation

Engineering Contradiction:
Improvestorage resourcesVSAvoiderror correction performance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent introduces asymmetric interleaving patterns where different rows or columns are treated differently in the write and read operations. This asymmetry breaks the regularity that limits row-column interleaving in higher order modulation, providing better error correction performance while maintaining low storage requirements through the structured yet irregular pattern design.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent dynamically changes interleaving parameters such as the number of rows, columns, and permutation patterns based on the modulation order and channel conditions. By adapting these parameters, the system achieves high error correction performance for higher order modulation without requiring fixed large storage resources, as the interleaving complexity scales with actual needs rather than maximum capacity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11139918B2Interleaving method and interleaving apparatus
Publication Date: 2021.10.05 HUAWEI TECH CO LTD
  • US11139918B2 patent drawing
  • US11139918B2 patent drawing
  • US11139918B2 patent drawing

AI summary

Various embodiments provide an interleaving method, to improve error correction performance of a polar code. In these embodiments, a first bit sequence is obtained. The first bit sequence includes L number of bits, and L is a positive integer. The L number of bits are then written into an interleaving matrix according to a preset write rule. The interleaving matrix includes C rows and R number of columns. C and R are positive integers. The L number of bits can be read from the interleaving matrix according to a preset read rule to obtain a second bit sequence. The second bit sequence includes L number of bits; and sending the second bit sequence.