Polar Code CRC Placement for Early-Termination Decoding
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Solution Overview
Problem
The finite-length performance of polar codes under successive cancellation decoding is not competitive with other modern channel coding schemes like LDPC and Turbo codes, and the use of CRC codes for error detection requires multiple polynomials for different list sizes, complicating design and implementation, while also leading to high decoding latency due to sequential decoding.
Innovation Solution
Generating additional CRC bits based on a given CRC polynomial to maintain error correcting capability and reduce latency, with the ability to place these bits closer to the beginning of the decoding process for early termination, using both non-recursive and recursive variants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRC code length is increased to maintain error detection capability for larger list sizes, then error detection performance is improved, but device complexity increases due to needing multiple CRC polynomials
Solution Approach 1:
A single CRC polynomial is designed to serve multiple functions: it generates CRC bits for error detection and simultaneously serves as a frozen bit pattern for the polar encoder. This universal approach eliminates the need for multiple specialized CRC polynomials for different list sizes, reducing device complexity while maintaining error detection performance through appropriate CRC bit placement in the decoding process
2Reliability
If CRC code length is increased to maintain error detection capability, then error detection performance is improved, but decoding latency increases
Solution Approach 1:
CRC bits are placed at positions that allow early verification during the sequential decoding process. By positioning CRC bits corresponding to frozen bits at strategic locations, the decoder can perform early termination checks before completing the full decoding of all information bits. This preliminary error detection capability reduces average decoding latency while maintaining robust error detection performance
3Device complexity
If sequential decoding is used to maintain low implementation complexity, then device complexity is reduced, but decoding latency increases
Solution Approach 1:
The polar encoder is configured with frozen bit patterns derived from CRC polynomials, enabling the sequential decoder to perform preliminary error checks at intermediate stages. This allows early termination when errors are detected, reducing average decoding latency without requiring complex parallel decoding structures. The frozen bit placement creates natural checkpoints in the sequential decoding process
4Reliability
If frozen bit pattern is optimized for error correction, then error correction performance is improved, but adaptability to different list sizes decreases
Solution Approach 1:
The system uses a family of CRC polynomials with varying degrees, where the polynomial degree can be selected based on the desired list size. By changing the parameter of polynomial degree rather than the entire polynomial structure, the system maintains optimized error correction performance through systematic frozen bit patterns while adapting to different SCL decoding list sizes. This parameter-based adaptation preserves the structural properties needed for error correction
Data Source
AI summary
According to some embodiments, a method in a wireless device comprises obtaining a set of information bits for wireless transmission and dividing the set of information bits into one or more subsets of information bits. For each subset, generating extra cyclic redundancy check (CRC) bits using a CRC polynomial capable of generating N CRC bits. The extra CRC bits for each subset comprise less than N CRC bits. The method further comprises: generating a final set of N or less CRC bits for the set of information bits using the CRC polynomial; generating a set of coded bits by encoding the set of information bits for wireless transmission, together with the extra CRC bits and the final set of CRC bits, using a polar encoder; and transmitting the set of coded bits using a wireless transmitter.