Polar-Code Interleaving Layout for Low-Latency Modulation

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Solution Overview

Problem

The increasing number of user equipment (UEs) and data volume in wireless communication systems pose challenges in efficiently using limited radio resources, leading to performance deterioration due to high latency and modulation order effects, especially when polar codes are used for channel coding.

Innovation Solution

A method involving a polar code-based transmission system with an interleaver having an odd number of columns, where bits are cyclically read out from specific columns to improve data transmission efficiency and reduce latency, while preventing performance deterioration associated with modulation order.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If polar codes are used for channel coding, then error correction performance is improved, but latency increases due to large code size requiring interleaving

Engineering Contradiction:
Improveerror correction performanceVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the polar code into multiple sub-blocks and processes them in parallel through multiple interleavers, dividing the large code processing task into smaller manageable units that can be handled simultaneously, thereby reducing overall latency while maintaining error correction performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts the number of interleavers and sub-block sizes based on code length and modulation order, optimizing the processing pipeline to balance between thorough error correction and minimal latency for different transmission conditions

Inventive Principle:
Principle #15Dynamics

2Reliability

If interleaver is used for polar code bits, then performance deterioration due to modulation order is prevented, but latency increases

Engineering Contradiction:
Improvemodulation performanceVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the bit sequence into multiple sub-blocks that are processed by parallel interleavers, reducing the time each bit spends in the interleaving process while collectively maintaining the full interleaving effect needed for modulation performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines multiple parallel interleaving operations into a unified processing pipeline where multiple interleavers work simultaneously on different sub-blocks, merging their outputs to achieve the same performance as a single large interleaver but with reduced latency

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If the number of user equipment and data volume increases, then communication capacity is improved, but efficient use of limited radio resources becomes difficult

Engineering Contradiction:
Improvecommunication capacityVSAvoidresource management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent changes key parameters including interleaver size, number of parallel interleavers, and sub-block segmentation based on modulation order and code length, optimizing resource utilization for different traffic conditions and user equipment densities

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements dynamic resource allocation where the interleaving structure adapts to current system conditions, adjusting the balance between parallel processing degree and interleaver size to efficiently manage radio resources under varying load conditions

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11258535B2Method and apparatus for transmitting information
Publication Date: 2022.02.22 LG ELECTRONICS INC
  • US11258535B2 patent drawing
  • US11258535B2 patent drawing
  • US11258535B2 patent drawing

AI summary

A transmission apparatus: encodes information into a first bit sequence, using a polar code; outputs a second bit sequence by inputting the first bit sequence to an interleaver; modulates the second bit sequence into modulation symbols according to a modulation order; and transmits the modulation symbols. The interleaver: has an odd number of columns; and is configured to cyclically read and output, from column k, bits stored in row n of the interleaver, and cyclically read and output, from column k+a, bits stored in row n+1 of the interleaver, wherein a represents an integer which is not 0.