Polar Code Rate Matching for Multi-Length Hardware Simplification
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Solution Overview
Problem
Polar code hardware exhibits high complexity due to the need for different hardware modules to accommodate various code lengths and rates, complicating the encoding process, especially in hybrid automatic repeat request mechanisms.
Innovation Solution
A rate matching method for Polar codes involves concatenating information and frozen bits, dividing them into a circular buffer using a predefined rule, and selecting a bit sequence of specified length from a predefined starting position, reducing complexity by adapting to different scenarios through interleaving functions and starting position determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different hardware modules are used for different code lengths and rates, then the Polar code can accommodate various transmission requirements, but the hardware complexity increases significantly
Solution Approach 1:
The patent implements a universal rate matching structure that can handle multiple code lengths (128, 256, 512, 1024 bits) and code rates through a single hardware module. The circular buffer and bit selection mechanism are designed to be configurable rather than dedicated to specific parameters, allowing the same hardware to adapt to different transmission requirements by changing control parameters such as the number of information bits K, code rate R, and resource block allocation.
Solution Approach 2:
The patent introduces dynamic configuration capabilities where the rate matching parameters (circular buffer size, bit selection pattern, starting position) can be adjusted based on the actual transmission requirements. The system dynamically selects which bits to transmit from the encoded sequence based on the desired code rate and resource allocation, rather than requiring separate hardware for each configuration.
2Adaptability or versatility
If multiple hardware modules are implemented for different scenarios, then various code lengths can be supported, but the encoding process becomes more complicated
Solution Approach 1:
The patent merges multiple rate matching functions into a single unified structure. Instead of having separate hardware modules for different code lengths (128, 256, 512, 1024), the invention combines them into one circular buffer-based rate matching unit that can handle all these cases. The encoding process is simplified by using a consistent bit selection and circular buffer approach regardless of the target code length.
Solution Approach 2:
The patent segments the encoded bit sequence into a circular buffer structure, allowing flexible selection of subsets of bits for transmission. The circular buffer is divided into segments that can be selectively accessed based on the required code rate and resource allocation, enabling efficient rate matching without requiring separate encoding paths for different scenarios.
3Device complexity
If a fixed hardware structure is used, then the design is simpler, but it cannot adapt to different code lengths and rates
Solution Approach 1:
The patent achieves adaptability through parameter configuration rather than structural changes. The circular buffer size, bit selection indices, and resource block mapping parameters can be adjusted based on the desired code length and rate. This allows a simple fixed hardware structure to accommodate varying transmission requirements by changing control parameters such as K (number of information bits), R (code rate), and the circular buffer read/write pointers.
Data Source
AI summary
Provided is a rate matching method and device for a Polar code. The method includes: concatenating K information bits and (N−K) frozen bits to generate a bit sequence of N bits, and encoding the bit sequence of N bits by means of a Polar code encoder with a generator matrix of size N×N to generate an initial bit sequence {S0, S1, . . . , SN−1} of N bits, where K and N are both positive integers and K is less than or equal to N; dividing a circular buffer into q parts, selecting bits from the initial bit sequence {S0, S1, . . . , SN−1} in a non-repeated manner, and writing the bits into the q parts of the circular buffer according to a predefined rule, where q=1, 2, 3 or 4; and sequentially selecting a bit sequence of a specified length from a predefined starting position in a bit sequence in the circular buffer and taking the bit sequence of the specified length as a bit sequence to be transmitted.