Polar Code Parity-Check Computation With Low-Complexity Encoding

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Solution Overview

Problem

The performance of polar codes in wireless communications is limited due to the ineffective computation of parity-check bits, which results in a reduced number of effective parity-check bits and increased computational complexity, especially when using a shift-register computation of length 5, leading to negligible performance benefits and significant delay.

Innovation Solution

A simple and low-complexity method for computing parity-check bits by performing modulo-2 addition of all data bits placed in front of each parity-check bit, or using a systematic block code on the least reliable data bits, which can be implemented using a size-1 shift register or recursive summation, to enhance the error performance of polar codes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If shift-register computation of length 5 is used for parity-check bits, then error detection capability is improved, but computational complexity and delay are significantly increased

Engineering Contradiction:

Improveerror detection capabilityVSAvoidcomputational complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts only the essential parity-check computation function from the complex shift-register mechanism. By using simple modulo-2 addition of data bits to generate parity-check bits, the solution removes unnecessary computational steps while retaining the core error detection capability, thereby reducing complexity without sacrificing reliability

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of using a length-5 shift register to compute parity-check bits (conventional approach), the patent inverts the approach by using a size-1 shift register with direct modulo-2 addition. This inversion simplifies the computation from multiple stages to a single stage, reducing both complexity and delay while maintaining error detection functionality

Inventive Principle:

Principle #13The other way round (Inversion)

2Reliability

If shift-register computation of length 5 is used for parity-check bits, then error detection capability is improved, but transmission delay is significantly increased

Engineering Contradiction:

Improveerror detection capabilityVSAvoidtransmission delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent skips the multiple computation stages of the length-5 shift register and rushes through the parity-check computation using direct modulo-2 addition. This single-stage computation completes the error detection setup much faster, reducing transmission delay while maintaining the ability to detect errors during decoding

Inventive Principle:

Principle #21Skipping (Rushing through)

Solution Approach 2:

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If more parity-check bits are computed using complex methods, then error detection capability is improved, but the number of effective parity-check bits is reduced

Engineering Contradiction:

Improveerror detection capabilityVSAvoidnumber of effective parity-check bits

Core Design Contradiction:

ReliabilityVSLoss of information

Solution Approach 1:

The patent employs a systematic block code where the parity-check bits are generated through self-service modulo-2 addition of data bits. This approach ensures that each parity-check bit is efficiently computed and contributes maximally to error detection, preventing the reduction of effective parity-check bits while maintaining strong error detection capability

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS11476873B2Simple parity-check bit computation for polar codes

Publication Date: 2022.10.18 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)

AI summary

Methods and systems described herein are directed to encoding information bits for transmission. The methods can include receiving a set of information bits (900) and determining a set of parity check bits (910). The set of information bits is concatenated with the set of parity check bits (920), and the information bits are polar encoded into a set of information bits and frozen bits (930). The encoded set of information bits is transmitted to a wireless receiver (940). In particular embodiments, each parity check bit in the set of parity check bits is the binary sum of the values of all bits in front of it. Other embodiments include generating a set of parity check bits based on a systematic block code on the least reliable bits of the set of information bits. The methods and systems described herein may be applied to 3GPP 5G mobile communication systems.