Polar Code Rate Matching Using Cyclic Cache Interleaver
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Solution Overview
Problem
Existing polar code rate matching methods require three distinct sets of hardware for puncturing, shortening, and repetition, leading to high hardware implementation complexity and a large occupied area due to the need for separate interleavers for each method.
Innovation Solution
A method and device that utilize a cyclic cache to store and read encoded bits using the same bit storage and different bit reading orders for both puncturing and repetition, allowing a single interleaver to implement both rate matching manners, thereby reducing hardware complexity and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three separate hardware interleavers are used for puncturing, shortening, and repetition rate matching methods, then each method can be implemented independently and correctly, but hardware complexity increases and occupied area becomes large
Solution Approach 1:
The patent applies universality by designing a single hardware interleaver that can perform multiple rate matching functions (puncturing, shortening, and repetition) through software configuration. Instead of having three separate hardware interleavers, one interleaver is configured via control signals to implement different rate matching operations, thereby reducing hardware complexity while maintaining functionality for all three methods
Solution Approach 2:
The patent merges the functionality of three separate rate matching hardware components into a single unified hardware interleaver. By combining puncturing, shortening, and repetition operations into one hardware structure that can be dynamically configured, the patent reduces the total number of hardware components and their interconnections, thus lowering hardware complexity and occupied area
2Adaptability or versatility
If three separate hardware interleavers are used for different rate matching methods, then each method can be implemented with dedicated hardware, but the occupied hardware area becomes large
Solution Approach 1:
The patent implements universality by creating a single hardware interleaver that can adapt to support all three rate matching methods (puncturing, shortening, repetition) through configurable control signals. This multi-functional approach allows the same hardware structure to serve multiple purposes, significantly reducing the total hardware area required compared to having three separate dedicated interleavers
Solution Approach 2:
The patent utilizes parameter changes by modifying the operational parameters of the single hardware interleaver (such as input/output mappings, control signal values, and configuration registers) to switch between different rate matching methods. This allows the hardware to adapt its behavior dynamically without requiring separate hardware structures for each method, thereby reducing the occupied area
Data Source
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AI summary
Embodiments of the application provide a method and device for polar code rate matching. The method includes: polar encoding according to a mother code length N and a rate matching manner, to obtain encoded bits after the polar encoding, where the rate matching manner is a first rate matching manner or a second rate matching manner, and N is a positive integer; storing, into a cyclic cache according to a bit storage order corresponding to the rate matching manner, the encoded bits, wherein the first rate matching manner and the second rate matching manner are corresponding to a same bit storage order; and reading, from the cyclic cache according to a bit reading order corresponding to the rate matching manner, an output sequence obtained after rate matching, wherein the first rate matching manner and the second rate matching manner are corresponding to different bit reading orders. According to the embodiments, hardware complexity and an area occupied by hardware can be reduced.