Polar Coding with Shared CRC-PC Register for Faster Decoding
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Solution Overview
Problem
Current polar coding methods for channel coding in communications technologies face challenges in simplifying time, space, and calculation complexities, particularly in error correction and decoding processes, due to separate performance of CRC and PC coding, which hinders parallel processing and increases false alarm rates.
Innovation Solution
The method involves performing CRC and PC coding simultaneously using a common cyclic shift register, allowing for parallel coding and decoding, and employing frozen check bits and CRC check bits to reduce complexity and latency, enabling early path selection during decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If CRC and PC coding are performed separately using separate hardware resources, then coding functionality is complete, but time complexity, space complexity, and calculation complexity increase
Solution Approach 1:
The patent merges CRC coding and PC coding into a single unified coding process that uses one shared hardware resource (cyclic shift register). The method combines the check bit generation of CRC with the frozen check bit generation of PC, allowing both coding functions to be performed simultaneously in parallel, thereby reducing hardware complexity while maintaining or improving coding efficiency
Solution Approach 2:
The cyclic shift register is designed to serve multiple functions: it generates both CRC check bits and PC frozen check bits, and is used in both encoding and decoding processes. This multi-functional design eliminates the need for separate dedicated hardware resources for each coding type, reducing overall system complexity
2Reliability
If separate coding processes are used for CRC and PC, then coding completeness is maintained, but decoding latency increases
Solution Approach 1:
The unified coding process performs both CRC and PC check bit generation in advance during the encoding phase, storing the results in the cyclic shift register. During decoding, these pre-computed check bits are immediately available for parallel verification, eliminating the need for sequential processing and reducing decoding latency while maintaining error correction reliability
3Adaptability or versatility
If separate hardware resources are allocated for CRC and PC coding, then functional completeness is achieved, but calculation complexity increases
Solution Approach 1:
The patent combines the calculation processes of CRC and PC into a single unified algorithm that operates on a shared cyclic shift register. The method integrates the polynomial division of CRC with the frozen check bit calculation of PC, allowing both to be computed simultaneously with reduced computational steps, thereby lowering calculation complexity while preserving the flexibility of both coding schemes
Data Source
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AI summary
A coding method, a decoding method, an apparatus, and a device are provided. The method includes: coding, by a sending device, an information bit sequence to obtain a coded bit sequence, where the coded bit sequence includes an information bit, a frozen bit, a CRC check bit, and a frozen check bit; and a value of the frozen check bit and a value of the CRC check bit are obtained by using a same cyclic shift register; performing, by the sending device, polar coding and rate matching on the coded bit sequence to obtain a to-be-sent rate-matched sequence; and sending, by the sending device, the rate-matched sequence. According to the method, time and space for coding calculation and decoding calculation can be effectively saved, and calculation complexity is reduced.