Polar Coding with Unified CRC-PC Checks for Low-Complexity Decoding
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Solution Overview
Problem
Current polar coding methods lack an efficient and convenient manner for error correction at the decoding end, leading to increased time, space, and calculation complexities due to separate processing of CRC and PC coding, and high false alarm rates in CRC-aided SCL decoders.
Innovation Solution
The proposed method performs polar coding and CRC coding simultaneously using a common cyclic shift register, allowing for parallel processing and early path selection, thereby simplifying the coding and decoding algorithms and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate processing of CRC and PC coding is performed, then error correction capability is maintained, but time complexity, space complexity, and calculation complexity increase
Solution Approach 1:
The patent merges CRC coding and PC coding into a unified coding process where both operations are performed simultaneously on the same bit sequence using a single cyclic shift register. This integration eliminates the need for separate processing stages, reducing time complexity, space complexity, and calculation complexity while maintaining the error correction capabilities of both CRC and PC codes.
Solution Approach 2:
The cyclic shift register is designed to serve multiple functions: it performs both CRC check operations and PC check operations within the same hardware structure. The register can be configured to execute different coding operations based on the same fundamental mechanism, thereby reducing device complexity and avoiding the need for separate dedicated hardware for each coding type.
2Reliability
If separate processing of CRC and PC coding is performed, then coding functionality is complete, but latency increases
Solution Approach 1:
The unified coding structure performs both CRC and PC operations in a single pass through the bit sequence, rather than sequentially processing each code type separately. This preliminary integration of operations eliminates redundant processing steps and reduces the overall time required for encoding, thereby reducing coding latency while maintaining complete coding functionality.
3Reliability
If CRC-aided SCL decoding is used, then decoding capability is enhanced, but false alarm rate increases
Solution Approach 1:
The patent introduces a unified check mechanism that acts as an intermediary between CRC and PC verification processes. This intermediate structure allows for coordinated validation of both code types, enabling the decoder to distinguish between genuine errors and false alarms more effectively, thereby reducing the false alarm rate while maintaining enhanced decoding capability.
Data Source
AI summary
A coding method, a decoding method, an apparatus, and a device are provided. The method includes: coding, by a sending device, an information bit sequence to obtain a coded bit sequence, where the coded bit sequence includes an information bit, a frozen bit, a CRC check bit, and a frozen check bit; and a value of the frozen check bit and a value of the CRC check bit are obtained by using a same cyclic shift register; performing, by the sending device, polar coding and rate matching on the coded bit sequence to obtain a to-be-sent rate-matched sequence; and sending, by the sending device, the rate-matched sequence. According to the method, time and space for coding calculation and decoding calculation can be effectively reduced, and calculation complexity is reduced.