Polar Code CRC Interleaving for Early-Termination Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The finite-length performance of polar codes under successive cancellation (SC) decoding is not competitive with other modem channel coding schemes like LDPC and Turbo codes, and the two-step decoding process with concatenated CRC codes increases latency without optimally accounting for the structure of both codes.
Innovation Solution
Implementing a specific interleaving pattern between a linear outer code (e.g., CRC) and a polar inner code, allowing early termination of decoding based on distributed CRC bits during the successive cancellation list (SCL) decoding process, while maintaining a low false-alarm rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two-step decoding process with concatenated CRC codes is used, then the finite-length performance of polar codes becomes competitive with LDPC and Turbo codes, but the decoding latency increases
Solution Approach 1:
The patent segments the CRC bits and distributes them to different positions within the code block rather than placing them all at the end. This segmentation allows the decoder to perform early termination checks at multiple points during the decoding process, reducing the average decoding latency while maintaining the error detection capability of the full CRC code.
Solution Approach 2:
The patent performs preliminary actions by placing CRC bits at strategic positions throughout the code block, enabling early error detection before the complete decoding process finishes. This allows the decoder to terminate early when errors are detected, avoiding the full decoding latency while maintaining reliability.
2Ease of operation
If CRC bits are placed at the end of the code block, then the decoding process is simple, but early termination is not possible and latency increases
Solution Approach 1:
The patent segments the CRC code into multiple distributed bits positioned throughout the code block. This segmentation enables the decoder to perform checks at intermediate points without complicating the overall decoding structure, achieving early termination while keeping the implementation relatively simple.
Solution Approach 2:
The distributed CRC bits act as intermediaries that provide error detection capability at multiple stages of the decoding process. These intermediate checkpoints allow early termination without requiring a complete decode, reducing latency while maintaining a straightforward decoding approach.
3Loss of time
If distributed CRC bits are used for early termination, then decoding latency is reduced, but the false-alarm rate may increase
Solution Approach 1:
The patent applies local quality by strategically positioning CRC bits at specific locations within the code block where they can provide effective error detection. The distribution pattern and positioning are optimized to minimize false alarms while enabling early termination, ensuring that each CRC bit location serves its purpose effectively.
Solution Approach 2:
The patent changes the parameter of CRC bit positioning from a single end-location to multiple distributed locations throughout the code block. This parameter change optimizes the balance between early termination capability and false-alarm rate by selecting specific positions that maximize error detection while minimizing premature terminations.
Data Source
AI summary
According to some embodiments, a method of operation of a wireless transmitter in a wireless communication network comprises: encoding a set of information carrying data bits u of length K with a linear outer code to generate a set of outer parity bits p along with the data bits u; interleaving the set of outer parity bits p and the data bits u using a predetermined interleaving mapping function that depends on the number of data bits K and is operable to distribute some bits of the set of parity bits p in front of some data bits u; and encoding the interleaved bits using a Polar encoder to generate a set of encoded bits x. Various interleaving mapping functions are disclosed.