Polar Code CRC Bit Interleaving for CA-SCL Path Selection
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Solution Overview
Problem
The performance of CA-polar codes in wireless communications is limited by the deletion of correct paths during CA-SCL decoding due to low metrics at intermediate nodes, which affects the overall decoding efficiency.
Innovation Solution
The proposed solution involves interleaving CRC encoded bits between information bits, using them as parity check bits, and setting frozen bits to agreed fixed values, thereby improving the CA-SCL decoding performance by increasing the probability of deleting incorrect paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If CA-SCL decoding is used to decode polar codes, then decoding performance can be improved through path search and metric evaluation, but correct paths may be deleted at intermediate nodes due to low metrics, reducing overall decoding reliability
Solution Approach 1:
The patent applies preliminary action by inserting CRC check bits at predetermined positions before the final CRC verification stage. These intermediate CRC bits perform preliminary error detection during the decoding process, allowing early identification and correction of incorrect paths before they reach the final decision node, thus preventing deletion of correct paths due to temporary metric dips
Solution Approach 2:
The patent uses intermediate CRC check bits as mediators between the received signal and the final decoding decision. These intermediary check bits provide additional verification points during the SCL decoding process, acting as a bridge that helps maintain correct path integrity by offering periodic validation without requiring complete re-decoding
2Device complexity
If frozen bits are set to fixed values (e.g., 0) to simplify encoding, then encoding complexity is reduced, but flexibility in adapting to different channel conditions is limited
Solution Approach 1:
The patent applies local quality by differentiating the treatment of frozen bits based on their positions and functions. While most frozen bits remain fixed at zero for simplicity, certain frozen bit positions are designated to carry specific control information or adapt to channel conditions. This allows the system to maintain low encoding complexity for the majority of bits while providing localized adaptability where needed
Solution Approach 2:
The patent makes frozen bits multi-functional by enabling them to serve both as traditional fixed-value bits for simplification and as adaptive elements for channel conditioning. The same frozen bit structure can operate in different modes depending on channel state, providing universal functionality that adapts to various communication scenarios without requiring separate encoding schemes
3Reliability
If all CRC bits are used for final verification, then error detection capability is maximized, but intermediate path validation during decoding is insufficient
Solution Approach 1:
The patent segments the CRC verification function into multiple stages: intermediate CRC checks distributed at predetermined positions during decoding, and a final CRC verification. This segmentation allows error detection to occur at multiple points in the decoding process rather than relying solely on a single final check, improving overall reliability without requiring a complete re-decoding pass
Solution Approach 2:
The patent performs preliminary error detection using intermediate CRC bits positioned throughout the decoding process. These preliminary checks identify and flag potential errors early, allowing the decoder to prune incorrect paths before reaching the final decision stage, thereby reducing the need for extensive final verification and optimizing the balance between reliability and decoding time
Data Source
AI summary
Embodiments of polar encoding/decoding methods and apparatuses are described. CRC encoding is performed on an information block to obtain a CRC encoded block with a length of B, where a CRC length is Lcrc, an information block length is K, and B=K+Lcrc. The CRC encoded block is interleaved. Lpc CRC bits in the interleaved encoded block are located between bits of the information block. Each CRC bit of the Lpc CRC bits is located after all bits checked by using the CRC bit. Lpc is an integer greater than 0 and less than Lcrc. The interleaved encoded block is mapped to information bits. A frozen bit is set to an agreed fixed value. Polar encoding is performed on the information bits and the frozen bit to obtain a polar encoded codeword to improve performance of a CA-polar code.