Polar Decoder Buffer Mapping for Faster SCL Path Management
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Solution Overview
Problem
Current polar decoders face inefficiencies in implementing polar decoding due to costly memory copy operations and complex memory allocation, particularly in handling LLR and bit memory for path killing and cloning in Successive Cancellation List (SCL) decoding.
Innovation Solution
The implementation of a polar decoder on a vector processor using a list-to-buffer mapping state register to manage memory operations, avoiding explicit memory copies by manipulating the state register to kill and clone paths, and employing this register to determine memory locations for LLR and bit updates, thereby simplifying memory management and improving throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If explicit memory copy operations are used to manage LLR and bit memory for path killing and cloning in SCL decoding, then path management can be implemented, but computational overhead increases and throughput decreases
Solution Approach 1:
The patent introduces a list-to-buffer mapping state register as an intermediary data structure that maps list indices to buffer locations. This register acts as a mediator between the decoding logic and memory operations, enabling path killing and cloning through simple index updates in the state register rather than complex memory copy operations. The state register contains mapping entries that associate each list path with its corresponding buffer location, allowing efficient redirection of memory access patterns.
Solution Approach 2:
The patent uses a state register that stores mapping information (indices) rather than copying actual data. When path cloning is needed, the state register is updated to point to new buffer locations, and when path killing is needed, the mapping is simply removed or invalidated. This indirect copying of indices in the state register is much more efficient than direct copying of LLR and bit buffer data.
2Productivity
If complex memory allocation operations are performed for path management, then path killing and cloning can be implemented, but computational overhead increases
Solution Approach 1:
The patent segments the memory management task by separating the state tracking (in the state register) from the actual data storage (in buffers). The state register is divided into multiple mapping entries, each corresponding to a list path, allowing independent management of each path's buffer location. This segmentation enables efficient path cloning by simply duplicating or redirecting individual mapping entries without affecting other paths.
Solution Approach 2:
The patent pre-allocates buffer spaces and pre-establishes the mapping structure in the state register before decoding begins. Buffer locations are reserved in advance, and the state register is initialized with default mappings. This preliminary setup eliminates the need for complex dynamic memory allocation during the actual path killing and cloning operations, reducing computational overhead during critical decoding phases.
3Productivity
If fixed hardware is used for polar decoding, then decoding performance can be optimized, but adaptability to different processing platforms is reduced
Solution Approach 1:
The patent designs a universal state register structure that can be implemented on various processing platforms including general-purpose vector processors, FPGAs, and ASICs. The list-to-buffer mapping concept is platform-agnostic and can be realized through different hardware or software mechanisms depending on the target platform. This universal approach allows the same decoding algorithm to achieve high efficiency across multiple platform types without requiring platform-specific customizations.
Solution Approach 2:
The patent employs a dynamic state register that can be configured and updated during runtime based on the specific decoding requirements and platform capabilities. The mapping entries in the state register can be dynamically modified to accommodate different code lengths, list sizes, and buffer configurations. This dynamic adaptability allows the system to optimize performance for different operating conditions while maintaining platform flexibility.
Data Source
AI summary
In some examples, a polar decoder for implementing polar decoding of a codeword can be configured to implement alogarithmic likelihood ratio (LLR), an even bit, and an odd bit buffer, respectively. The polar decoder can be configured to employ a list-to-buffer mapping state register for the LLR buffer for loading LLR values for each path at a given stage of a decoding graph. The polar decoder can be configured to update and store LLR values for each path at the given stage. The polar decoder can be configured to employ a list-to-buffer mapping state register for the even bit buffer for loading even bit values from the even bit buffer and loading odd bit values from the odd bit buffer, and updating even or odd bit values for each path at the given stage of the decoding graph.