Polar Decoder Column Merging for Low-Latency Parallel Decoding
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Solution Overview
Problem
Existing polar decoders suffer from poor hardware efficiency and high memory bandwidth requirements due to limited parallelism and excessive memory usage, which restricts their ability to fully exploit parallel processing opportunities and increases latency.
Innovation Solution
A novel polar decoder architecture that processes multiple consecutive stages in parallel, decomposing the polar code graph into columns with reduced memory requirements and a simplified mechanism for propagating partial sum bits, allowing flexible adaptation to different block sizes and parameterizations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional polar decoder architecture processes stages sequentially with dedicated hardware for each XOR operation, then decoding accuracy is maintained, but hardware efficiency deteriorates and latency increases
Solution Approach 1:
The patent merges multiple consecutive stages of the polar code graph into a single processing unit. Instead of implementing each stage separately with dedicated hardware, the decoder combines stages and processes them in parallel using a unified set of processing elements, thereby improving hardware efficiency and reducing latency while maintaining decoding accuracy
Solution Approach 2:
The patent segments the polar code graph into columns rather than processing it stage-by-stage. By organizing the graph structure into vertical columns and processing multiple columns in parallel, the decoder exploits spatial parallelism opportunities that were previously unavailable in sequential stage-based architectures
2Productivity
If memory is used to store intermediate results at each stage interface, then data dependencies are satisfied, but memory bandwidth requirements increase and hardware efficiency decreases
Solution Approach 1:
The patent performs preliminary organization of data flow through the column-based structure, arranging computations so that intermediate results are naturally available when needed without requiring extensive memory storage. The column processing order is designed to minimize memory writes and reads by exploiting the inherent data flow patterns in polar decoding
3Adaptability or versatility
If dedicated hardware is allocated for each processing unit in the graph, then processing speed is maintained, but hardware resource utilization deteriorates when block size varies
Solution Approach 1:
The patent implements universal processing units that can handle multiple stages through time-multiplexing. The same hardware resources are reused across different stages and different block sizes, allowing the decoder to adapt flexibly to varying communication channel requirements while maintaining high processing throughput through efficient resource utilization
Data Source
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AI summary
A polar decoder kernal (111) is described. The polar decoder kernal (111) is configured to: receive one or more soft bits from a soft kernal encoded block (113) having a block size of N and output one or more recovered kernal information bits from a recovered kernal information block (114) having a block size of N. The polar decoder kernal (111) comprises a decomposition of a polar code graph (201, 202, 203) into an arbitrary number of columns (1701, 1702) depending on the kernal block size N.