Polar Decoder Higher-Order Kernels for Fewer LLR Stages
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Solution Overview
Problem
Current polar coding techniques for wireless communications require a large number of decoding stages and memory resources, making them inefficient for practical implementation, especially in 5G New Radio (NR) systems, due to the need for log2N Log Likelihood Ratio (LLR) stages in decoding N-bit codewords.
Innovation Solution
The method involves reducing the number of LLR stages by using higher-order polar decoding kernels, such as A4 or A8 kernels, which combine multiple lower-order kernels to perform decoding in fewer than log2N stages, thereby reducing latency and memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional polar decoding using log2N LLR stages is used, then decoding accuracy is maintained, but decoding latency and memory usage increase
Solution Approach 1:
The patent combines multiple lower-order polar decoding kernels (e.g., A2 kernels) into a single higher-order polar decoding kernel (e.g., A4 or A8 kernel). This merging reduces the total number of LLR stages from log2N to fewer than log2N stages while maintaining decoding accuracy, directly addressing the technical contradiction by reducing decoding latency without sacrificing performance.
Solution Approach 2:
The patent segments the conventional log2N LLR stages into groups that can be processed by higher-order kernels. By dividing the decoding process into fewer, more complex stages, the patent reduces the overall number of stages while maintaining the necessary computational depth for accurate decoding, thus reducing latency.
2Reliability
If conventional polar decoding is implemented, then decoding accuracy is achieved, but memory resources are consumed
Solution Approach 1:
By merging multiple lower-order kernels into higher-order kernels, the patent reduces the number of intermediate LLR values that need to be stored in memory. The higher-order kernels process multiple inputs simultaneously, reducing the memory footprint required for storing intermediate decoding states while maintaining decoding accuracy.
3Productivity
If higher-order polar decoding kernels are used, then decoding latency is reduced, but kernel complexity increases
Solution Approach 1:
The patent changes the parameters of the polar decoding kernel by transitioning from lower-order kernels (A2) to higher-order kernels (A4, A8). This parameter change increases the processing capability of each kernel stage, allowing fewer stages to achieve the same decoding efficiency, thus improving productivity despite increased individual kernel complexity.
Data Source
AI summary
In reduced-stage polar decoding, a received word that is based on an N-bit codeword of a polar code is decoded using fewer than log2N Log Likelihood Ratio (LLR) stages. Decoding uses a reduced stage decoding configuration. In an embodiment, such a configuration includes at least one higher-order LLR stage with nodes implementing functions that are based on a combination of lower-order polar code kernels.