Polar Code Decoder Circuit for Low-Latency LLR Processing
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Solution Overview
Problem
Conventional polar code decoders face challenges with high latency and low throughput due to their serial processing nature and complex logic stages, which limits their performance in applications like 5G wireless devices.
Innovation Solution
A decoder architecture that combines F and G functions into a single processing unit with reduced logic stages, using a control circuit and lookup tables to select between F and G functions, and employs a multiplexer to reduce latency and increase throughput by processing input vectors in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional polar code decoders use serial processing with complex logic stages, then decoding accuracy is maintained, but latency increases and throughput decreases
Solution Approach 1:
The decoder processes log-likelihood ratio vectors by segmenting the computation into distinct functional blocks: absolute value extraction units, sign extraction units, adder/subtractor units, and multiplexer units. Each block handles a specific operation, allowing parallel processing of multiple input vectors simultaneously while maintaining decoding accuracy.
Solution Approach 2:
The patent transitions from serial processing to parallel processing by adding a temporal dimension to the computation. Multiple input vectors are processed simultaneously across multiple processing paths, with each path containing the full sequence of logic stages. This dimensional expansion increases throughput without requiring each individual path to be simpler.
2Loss of time
If conventional polar code decoders use serial processing, then device complexity is reduced, but latency increases
Solution Approach 1:
The decoder performs preliminary extraction of absolute values and signs from input log-likelihood ratios in parallel before the main computation stages. This preliminary processing prepares data in advance for subsequent addition/subtraction and selection operations, reducing the critical path delay and overall latency of the decoding process.
Solution Approach 2:
The patent implements continuous parallel processing where multiple input vectors flow through the decoder simultaneously in pipelined fashion. While one vector is being processed through early stages, other vectors are being processed through later stages, ensuring continuous utilization of all logic stages and maximizing throughput without increasing latency per vector.
3Adaptability or versatility
If a multiplexer is used to select between F and G functions, then adaptability is improved, but device complexity increases
Solution Approach 1:
The decoder employs a universal processing unit that can perform both F-function and G-function operations by selectively enabling different computational paths through the multiplexer. The same adder/subtractor and absolute value extraction units serve both function types, reducing overall device complexity while maintaining full adaptability to different Polar code configurations.
Data Source
AI summary
Apparatuses and methods relating generally to a decoder. In an apparatus, a control circuit receives first-third sign signals, a partial sum signal, a function select signal, and a carry signal as an input vector to provide an output sign and a vector select. A select generation circuit receives the first and second sign signals and the partial sum signal to provide an add/subtract select signal. A subtractor subtracts from a first absolute value signal a second absolute value signal to provide the third sign signal and a difference signal. Responsive to the add/subtract select signal, an adder/subtractor either adds or subtracts the first absolute value signal to or from the second absolute value signal to provide the carry signal and a sum/difference signal. A multiplexer selects from the first and second absolute value signals, the difference signal, and the sum/difference signal a selected value signal responsive to the vector select.